forked from github/verilator
91 lines
2.4 KiB
Systemverilog
91 lines
2.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2011 by Wilson Snyder.
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module t_embed1_wrap (/*AUTOARG*/
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// Outputs
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bit_out, vec_out, wide_out, did_init_out,
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// Inputs
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clk, bit_in, vec_in, wide_in, is_ref
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);
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/*AUTOINOUTMODULE("t_embed1_child")*/
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// Beginning of automatic in/out/inouts (from specific module)
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output bit bit_out;
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output bit [30:0] vec_out;
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output bit [123:0] wide_out;
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output bit did_init_out;
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input clk;
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input bit_in;
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input [30:0] vec_in;
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input [123:0] wide_in;
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input is_ref;
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// End of automatics
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`ifdef verilator
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// Import $t_embed_child__initial etc as a DPI function
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`endif
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//TODO would like __'s as in {PREFIX}__initial but presently illegal for users to do this
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import "DPI-C" context function void t_embed_child_initial();
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import "DPI-C" context function void t_embed_child_final();
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import "DPI-C" context function void t_embed_child_eval();
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import "DPI-C" context function void t_embed_child_io_eval
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(
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//TODO we support bit, but not logic
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input bit clk,
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input bit bit_in,
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input bit [30:0] vec_in,
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input bit [123:0] wide_in,
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input bit is_ref,
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output bit bit_out,
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output bit [30:0] vec_out,
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output bit [123:0] wide_out,
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output bit did_init_out);
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initial begin
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// Load all values
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t_embed_child_initial();
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end
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// Only if system verilog, and if a "final" block in the code
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final begin
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t_embed_child_final();
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end
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bit _temp_bit_out;
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bit _temp_did_init_out;
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bit [30:0] _temp_vec_out;
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bit [123:0] _temp_wide_out;
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always @* begin
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t_embed_child_io_eval(
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clk,
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bit_in,
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vec_in,
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wide_in,
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is_ref,
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_temp_bit_out,
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_temp_vec_out,
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_temp_wide_out,
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_temp_did_init_out
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);
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// TODO might eliminate these temporaries
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bit_out = _temp_bit_out;
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did_init_out = _temp_did_init_out;
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end
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// Send all variables every cycle,
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// or have a sensitivity routine for each?
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// How to make sure we call eval at end of variable changes?
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// #0 (though not verilator compatible!)
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// TODO for now, we know what changes when
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always @ (posedge clk) begin
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vec_out <= _temp_vec_out;
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wide_out <= _temp_wide_out;
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end
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endmodule
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