forked from github/verilator
24 lines
732 B
Systemverilog
24 lines
732 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t;
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function automatic string foo(int i);
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return $sformatf("'%d'", i); // %0d does not work here
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endfunction
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real r = 1.234;
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string bar = foo(1);
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localparam string pbar = foo(1);
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initial begin
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$write("String: "); $display("' 1'");
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$write("foo(1): "); $display(foo(1));
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$write("s f(1): "); $display("%s", foo(1));
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$write("s parm: "); $display("%s", pbar);
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$write("s strg: "); $display("%s", bar);
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$write("r: "); $display(r);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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