forked from github/verilator
46 lines
1.3 KiB
Systemverilog
46 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2017 by Wilson Snyder.
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module t (/*AUTOARG*/);
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initial begin
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$display("Merge:");
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$write("This ");
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$write("should ");
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$display("merge");
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$display("f");
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$display(" a=%m");
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$display(" b=%m");
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$display(" pre");
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$display(" t=%0d",$time);
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$display(" t2=%0d",$time);
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$display(" post");
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$display(" t3=%0d",$time);
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$display(" t4=%0d t5=%0d",$time,$time,$time);
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$display("m");
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$display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time);
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$display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time);
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$display("mm");
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$display("");
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$write("f");
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$write(" a=%m");
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$write(" b=%m");
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$write(" pre");
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$write(" t=%0d",$time);
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$write(" t2=%0d",$time);
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$write(" post");
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$write(" t3=%0d",$time);
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$write(" t4=%0d t5=%0d",$time,$time,$time);
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$write("m");
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$write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time);
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$write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time);
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$display("mm");
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$write("\n*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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