forked from github/verilator
52912c6329
- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
17 lines
455 B
Systemverilog
17 lines
455 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t;
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reg [40:0] disp; initial disp = 41'ha_bbbb_cccc;
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initial begin
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// Display formatting
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$display("%x"); // Too few
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$display("%x",disp,disp); // Too many
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$display("%q"); // Bad escape
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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