forked from github/verilator
28 lines
1.1 KiB
Systemverilog
28 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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module t (/*AUTOARG*/);
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initial begin
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int i;
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string a [string];
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string k;
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string v;
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a = '{ "f": "fooed", "b": "bared", default: "defaulted" };
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i = a.size(); `checkh(i, 2); // Default doesn't count
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v = a["f"]; `checks(v, "fooed");
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v = a["b"]; `checks(v, "bared");
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v = a["NEXISTS"]; `checks(v, "defaulted");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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