forked from github/verilator
599d23697d
This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
15 lines
1.0 KiB
Plaintext
15 lines
1.0 KiB
Plaintext
%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:15:15: Signal unoptimizable: Circular combinational logic: 't.x'
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15 | wire [2:0] x;
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| ^
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... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest
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... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
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t/t_unoptflat_simple_2.v:15:15: Example path: t.x
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t/t_unoptflat_simple_2.v:17:18: Example path: ASSIGNW
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t/t_unoptflat_simple_2.v:15:15: Example path: t.x
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... Widest variables candidate to splitting:
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t/t_unoptflat_simple_2.v:15:15: t.x, width 3, circular fanout 2, can split_var
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... Candidates with the highest fanout:
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t/t_unoptflat_simple_2.v:15:15: t.x, width 3, circular fanout 2, can split_var
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... Suggest add /*verilator split_var*/ to appropriate variables above.
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%Error: Exiting due to
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