forked from github/verilator
14 lines
662 B
Plaintext
14 lines
662 B
Plaintext
%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
|
|
: ... In instance t
|
|
w = '0;
|
|
^
|
|
%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:23: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
|
|
: ... In instance t
|
|
o = '0;
|
|
^
|
|
%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
|
|
: ... In instance t
|
|
oa = '0;
|
|
^~
|
|
%Error: Exiting due to
|