forked from github/verilator
28 lines
676 B
Systemverilog
28 lines
676 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Driss Hafdi
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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typedef logic [15:0] count_t;
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typedef bit [31:0] bit_int_t;
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localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}};
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localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)};
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initial begin
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if (count_bits[0] != 16) $stop;
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if (count_bits[1] != 16) $stop;
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if (count_bitsc[0] != 16) $stop;
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if (count_bitsc[1] != 16) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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