forked from github/verilator
18 lines
457 B
Systemverilog
18 lines
457 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2009 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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module t ();
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// Can't handle time (yet?)
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import "DPI-C" dpii_fa_bit = function logic [2:0] oth_f_int1(input time i);
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initial begin
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$stop;
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end
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endmodule
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