forked from github/verilator
53 lines
1.4 KiB
Systemverilog
53 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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clk
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);
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input clk;
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function bit test_find;
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string bar[$];
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string found[$];
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bar.push_back("baz");
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bar.push_back("qux");
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found = bar.find(x) with (x == "baz");
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return found.size() == 1;
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endfunction
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function static bit test_find_index;
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int q[$] = {1, 2, 3, 4};
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int found[$] = q.find_index(x) with (x <= 2);
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return found.size() == 2;
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endfunction
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function static bit test_find_first_index;
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int q[] = {1, 2, 3, 4, 5, 6};
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int first_even_idx[$] = q.find_first_index(x) with (x % 2 == 0);
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return first_even_idx[0] == 1;
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endfunction
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function automatic bit test_sort;
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int q[] = {-5, 2, -3, 0, 4};
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q.sort(x) with (x >= 0 ? x : -x);
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return q[1] == 2;
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endfunction
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always @(posedge clk) begin
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bit [3:0] results = {test_find(), test_find_index(),
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test_find_first_index(), test_sort()};
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if (results == '1) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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$write("Results: %b\n", results);
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$stop;
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end
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end
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endmodule
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