forked from github/verilator
d4f7f5297a
Includes `timescale, $printtimescale, $timeformat. VL_TIME_MULTIPLIER, VL_TIME_PRECISION, VL_TIME_UNIT have been removed and the time precision must now match the SystemC time precision. To get closer behavior to older versions, use e.g. --timescale-override "1ps/1ps".
52 lines
1.3 KiB
Plaintext
52 lines
1.3 KiB
Plaintext
$version Generated by VerilatedVcd $end
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$date Tue Jul 24 18:46:01 2012
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$end
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$timescale 1ps $end
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$scope module top $end
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$var wire 1 # clk $end
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$var wire 1 $ reset_l $end
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$scope module t $end
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$var wire 1 # clk $end
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$var wire 1 % inmod $end
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$var wire 32 & rawmod [31:0] $end
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$var wire 1 $ reset_l $end
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$scope module genblk1 $end
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$var wire 32 ' ingen [31:0] $end
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$upscope $end
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$scope module unnamedblk1 $end
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$var wire 32 ( upa [31:0] $end
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$scope module d3nameda $end
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$var wire 32 ) d3a [31:0] $end
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$upscope $end
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$upscope $end
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$scope module unnamedblk2 $end
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$var wire 32 * b2 [31:0] $end
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$scope module b3named $end
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$var wire 32 + b3n [31:0] $end
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$upscope $end
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$scope module unnamedblk3 $end
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$var wire 32 , b3 [31:0] $end
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$scope module unnamedblk4 $end
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$var wire 32 - b4 [31:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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