forked from github/verilator
25 lines
580 B
Systemverilog
25 lines
580 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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integer p_i;
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initial begin
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// BAD: Missing argument
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if ($value$plusargs("NOTTHERE", p_i)!==0) $stop;
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// BAD: Bad letter
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if ($value$plusargs("INT=%z", p_i)!==0) $stop;
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// BAD: Multi letter
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if ($value$plusargs("INT=%x%x", p_i)!==0) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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