forked from github/verilator
5b3717b369
This patch normalizes what the tests do before exiting. After this change each test should call final on the top module and explicitly free the top module object before exiting.
63 lines
1.5 KiB
C++
63 lines
1.5 KiB
C++
// -*- mode: C++; c-file-style: "cc-mode" -*-
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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#include <cstdlib>
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#include <verilated.h>
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#include "Vt_mem_slot.h"
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unsigned int Array[3];
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unsigned int StepSim(Vt_mem_slot* sim, unsigned int slot, unsigned int bit, unsigned int val,
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unsigned int rslot) {
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#ifdef TEST_VERBOSE
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printf("StepSim: slot=%u bit=%u val=%u rslot=%u\n", slot, bit, val, rslot);
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#endif
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sim->SlotIdx = slot;
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sim->BitToChange = bit;
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sim->BitVal = val;
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sim->SlotToReturn = rslot;
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sim->Clk = 0;
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sim->eval();
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sim->Clk = 1;
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sim->eval();
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if (sim->OutputVal != Array[rslot]) {
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printf("%%Error: got %x - expected %x\n", sim->OutputVal, Array[rslot]);
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exit(1);
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}
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if (val)
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Array[slot] |= (1 << bit);
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else
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Array[slot] &= ~(1 << bit);
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return sim->OutputVal;
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}
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int main(int argc, char* argv[]) {
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Vt_mem_slot* sim = new Vt_mem_slot;
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int slot, bit, i;
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Verilated::debug(0);
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// clear all bits in the array
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for (slot = 0; slot < 3; slot++)
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for (bit = 0; bit < 2; bit++) //
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StepSim(sim, slot, bit, 0, 0);
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printf("\nTesting\n");
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for (i = 0; i < 100; i++) //
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StepSim(sim, random() % 3, random() % 2, random() % 2, random() % 3);
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sim->final();
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VL_DO_DANGLING(delete sim, sim);
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printf("*-* All Finished *-*\n");
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}
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