forked from github/verilator
67 lines
1.4 KiB
Systemverilog
67 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: SystemVerilog interface test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Thierry Tambe.
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input logic clk,
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output logic HRESETn
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);
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int primsig[3];
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ahb_slave_intf iinst[3] (primsig[2:0]);
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sub sub01 [2] (.clk, .infc(iinst[0:1]));
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sub sub2 (.clk, .infc(iinst[2]));
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initial begin
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primsig[0] = 30;
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primsig[1] = 31;
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primsig[2] = 32;
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iinst[0].data = 10;
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iinst[1].data = 11;
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iinst[2].data = 12;
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end
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int cyc = 0;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 10) begin
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if (iinst[0].primsig != 30) $stop;
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if (iinst[1].primsig != 31) $stop;
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if (iinst[2].primsig != 32) $stop;
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if (iinst[0].data != 10) $stop;
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if (iinst[1].data != 11) $stop;
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if (iinst[2].data != 12) $stop;
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if (sub01[0].internal != 10) $stop;
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if (sub01[1].internal != 11) $stop;
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if (sub2.internal != 12) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub
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(
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input logic clk,
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ahb_slave_intf infc
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);
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int internal;
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always_comb internal = infc.data;
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endmodule
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interface ahb_slave_intf
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(
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input int primsig
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);
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int data;
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endinterface
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