forked from github/verilator
54 lines
1.2 KiB
Systemverilog
54 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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reg [1:0] reg_i;
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reg [1049:0] pad0;
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reg [1049:0] reg_o;
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reg [1049:0] spad1;
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/*AUTOWIRE*/
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always_comb begin
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if (reg_i[1] == 1'b1)
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reg_o = {986'd0, 64'hffff0000ffff0000};
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else if (reg_i[0] == 1'b1)
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reg_o = {64'hffff0000ffff0000, 986'd0};
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else
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reg_o = 1050'd0;
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end
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 0) begin
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reg_i <= 2'b00;
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pad0 <= '1;
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spad1 <= '1;
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end
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else if (cyc == 1) begin
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reg_i <= 2'b01;
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end
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else if (cyc == 2) begin
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if (reg_o != {64'hffff0000ffff0000, 986'd0}) $stop;
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reg_i <= 2'b10;
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end
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else if (cyc == 99) begin
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if (reg_o != {986'd0, 64'hffff0000ffff0000}) $stop;
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if (pad0 != '1) $stop;
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if (spad1 != '1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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