forked from github/verilator
39 lines
731 B
Systemverilog
39 lines
731 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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clk, in
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);
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input clk;
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input [2:0] in;
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output [2:0] out;
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logic [2:0] r_in;
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always_ff @ (posedge clk) r_in <= in;
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flop p0 (.clk(clk), .d(r_in[0]), .q(out[0]));
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flop p2 (.clk(r_in[1]), .d(clk), .q(out[1]));
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flop p1 (.clk(clk), .d(r_in[2]), .q(out[2]));
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endmodule
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module flop
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(
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input d,
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input clk,
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output logic q);
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// verilator no_inline_module
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always_ff @ (posedge clk) begin
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q <= d;
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end
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endmodule
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