forked from github/verilator
0110f0193e
git-svn-id: file://localhost/svn/verilator/trunk/verilator@1037 77ca24e4-aefa-0310-84f0-b9a241c72d87
19 lines
362 B
Verilog
19 lines
362 B
Verilog
// $Id$
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// DESCRIPTION: Verilator: Verilog Test module
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module t;
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initial begin
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`ifndef GOT_DEF1
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$write("%%Error: NO GOT_DEF1\n"); $stop;
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`endif
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`ifndef GOT_DEF2
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$write("%%Error: NO GOT_DEF2\n"); $stop;
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`endif
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`ifdef NON_DEF
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$write("%%Error: NON_DEF\n"); $stop;
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`endif
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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