forked from github/verilator
61 lines
1.4 KiB
Verilog
61 lines
1.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
|
// without warranty, 2012 by Wilson Snyder.
|
|
|
|
module t (/*AUTOARG*/
|
|
// Inputs
|
|
clk
|
|
);
|
|
input clk;
|
|
|
|
integer cyc=0;
|
|
reg [63:0] crc;
|
|
reg [63:0] sum;
|
|
|
|
// Test:
|
|
tri t;
|
|
bufif1 (t, crc[1], cyc[1:0]==2'b00);
|
|
bufif1 (t, crc[2], cyc[1:0]==2'b10);
|
|
|
|
tri0 t0;
|
|
bufif1 (t0, crc[1], cyc[1:0]==2'b00);
|
|
bufif1 (t0, crc[2], cyc[1:0]==2'b10);
|
|
|
|
tri1 t1;
|
|
bufif1 (t1, crc[1], cyc[1:0]==2'b00);
|
|
bufif1 (t1, crc[2], cyc[1:0]==2'b10);
|
|
|
|
wire [63:0] result = {59'h0, t1, 3'h0, t0};
|
|
|
|
// Test loop
|
|
always @ (posedge clk) begin
|
|
`ifdef TEST_VERBOSE
|
|
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
|
|
`endif
|
|
cyc <= cyc + 1;
|
|
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
|
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
|
|
if (cyc==0) begin
|
|
// Setup
|
|
crc <= 64'h5aef0c8d_d70a4497;
|
|
sum <= 64'h0;
|
|
end
|
|
else if (cyc<10) begin
|
|
sum <= 64'h0;
|
|
end
|
|
else if (cyc<90) begin
|
|
end
|
|
else if (cyc==99) begin
|
|
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
|
|
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
|
// What checksum will we end up with (above print should match)
|
|
`define EXPECTED_SUM 64'h14f90df4eab2c499
|
|
if (sum !== `EXPECTED_SUM) $stop;
|
|
$write("*-* All Finished *-*\n");
|
|
$finish;
|
|
end
|
|
end
|
|
|
|
endmodule
|