forked from github/verilator
47 lines
1.5 KiB
Systemverilog
47 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog example module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// ======================================================================
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// This is intended to be a complex example of several features, please also
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// see the simpler examples/make_hello_c.
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module top
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(
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// Declare some signals so we can see how I/O works
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input clk,
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input reset_l,
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output wire [1:0] out_small,
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output wire [39:0] out_quad,
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output wire [69:0] out_wide,
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input [1:0] in_small,
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input [39:0] in_quad,
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input [69:0] in_wide
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);
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// Connect up the outputs, using some trivial logic
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assign out_small = ~reset_l ? '0 : (in_small + 2'b1);
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assign out_quad = ~reset_l ? '0 : (in_quad + 40'b1);
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assign out_wide = ~reset_l ? '0 : (in_wide + 70'b1);
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// And an example sub module. The submodule will print stuff.
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sub sub (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.reset_l (reset_l));
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// Print some stuff as an example
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initial begin
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if ($test$plusargs("trace") != 0) begin
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$display("[%0t] Tracing to logs/vlt_dump.vcd...\n", $time);
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$dumpfile("logs/vlt_dump.vcd");
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$dumpvars();
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end
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$display("[%0t] Model running...\n", $time);
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end
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endmodule
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