forked from github/verilator
43 lines
1.1 KiB
Systemverilog
43 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// ======================================================================
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module sub
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(
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input clk,
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input reset_l
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);
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// Example counter/flop
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reg [31:0] count_c;
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always_ff @ (posedge clk) begin
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if (!reset_l) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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count_c <= 32'h0;
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// End of automatics
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end
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else begin
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count_c <= count_c + 1;
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if (count_c >= 3) begin
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// This write is a magic value the Makefile uses to make sure the
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// test completes successfully.
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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// An example assertion
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always_ff @ (posedge clk) begin
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AssertionExample: assert (!reset_l || count_c<100);
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end
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// And example coverage analysis
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cover property (@(posedge clk) count_c==3);
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endmodule
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