forked from github/verilator
47 lines
1.4 KiB
C++
47 lines
1.4 KiB
C++
// DESCRIPTION: Verilator: Verilog example module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2017 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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//======================================================================
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// Include common routines
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#include <verilated.h>
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// Include model header, generated from Verilating "top.v"
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#include "Vtop.h"
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int main(int argc, char** argv) {
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// See a similar example walkthrough in the verilator manpage.
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// This is intended to be a minimal example. Before copying this to start a
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// real project, it is better to start with a more complete example,
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// e.g. examples/c_tracing.
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// Construct a VerilatedContext to hold simulation time, etc.
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VerilatedContext* contextp = new VerilatedContext;
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// Pass arguments so Verilated code can see them, e.g. $value$plusargs
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// This needs to be called before you create any model
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contextp->commandArgs(argc, argv);
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// Construct the Verilated model, from Vtop.h generated from Verilating "top.v"
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Vtop* top = new Vtop{contextp};
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// Simulate until $finish
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while (!contextp->gotFinish()) {
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// Evaluate model
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top->eval();
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}
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// Final model cleanup
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top->final();
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// Destroy model
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delete top;
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// Return good completion status
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return 0;
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}
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