forked from github/verilator
598 lines
23 KiB
ReStructuredText
598 lines
23 KiB
ReStructuredText
.. Copyright 2003-2023 by Wilson Snyder.
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.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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*******************
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Language Extensions
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*******************
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The following additional constructs are the extensions Verilator supports
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on top of standard Verilog code. Using these features outside of comments
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or "`ifdef`"'s may break other tools.
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.. option:: `__FILE__
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The :option:`\`__FILE__` define expands to the current filename as a
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string, like C++'s __FILE__. This Verilator feature, added in 2006, was
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incorporated into IEEE 1800-2009.
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.. option:: `__LINE__
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The :option:`\`__LINE__` define expands to the current filename as a
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string, like C++'s __LINE__. This Verilator feature added in 2006 was
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incorporated into IEEE 1800-2009.
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.. option:: `error [string]
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This will report an error when encountered, like C++'s #error.
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.. option:: """ [string] """
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A triple-quoted block specifies a string that may include newlines and
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single quotes. This extension is experimental and may be removed
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without deprecation.
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.. option:: $c([string], ...);
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The string will be embedded directly in the output C++ code at the point
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where the surrounding Verilog code is compiled. It may either be a
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standalone statement (with a trailing ; in the string), or a function
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that returns up to a 32-bit number (without a trailing ;). This can be
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used to call C++ functions from your Verilog code.
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String arguments will be put directly into the output C++ code, except
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the word 'this' (i.e.: the object pointer) might be replaced with a
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different pointer as Verilator might implement logic with non-member
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functions. For this reason, any references to class members must be made
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via an explicit 'this->' pointer dereference.
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Expression arguments will have the code to evaluate the expression
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inserted. Thus to call a C++ function, :code:`$c("func(",a,")")` will
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result in :code:`func(a)` in the output C++ code. For input arguments,
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rather than hard-coding variable names in the string
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:code:`$c("func(a)")`, instead pass the variable as an expression
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::code:`$c("func(",a,")")`. This will allow the call to work inside
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Verilog functions where the variable is flattened out and enable other
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optimizations.
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Verilator does not use any text inside the quotes for
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ordering/scheduling. If you need the $c to be called at a specific
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time, e.g., when a variable changes, then the $c must be under an
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appropriate sensitivity statement, e.g.,
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:code:`always @(posedge clk) $c("func()")` to call it on every edge, or,
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e.g., :code:`always @* c("func(",a,")")` to call it when :code:`a`
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changes (the latter working because :code:`a` is outside the quotes).
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If you will be reading or writing any Verilog variables inside the C++
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functions, the Verilog signals must be declared with
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:option:`/*verilator&32;public*/` metacomments.
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You may also append a number to $c, which specifies the bit width of
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the output, e.g., :code:`signal_32_bits = $c32("...");`. This allows for
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compatibility with other simulators, which require a differently named
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PLI function name for each different output width.
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.. option:: $display, $write, $fdisplay, $fwrite, $sformat, $swrite
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Format arguments may use C fprintf sizes after the % escape. Per the
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Verilog standard, %x prints a number with the natural width, and %0x
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prints a number with minimum width. Verilator extends this so %5x
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prints 5 digits per the C standard. This extension was standardized into
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1800-2009.
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.. option:: $timeprecision
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Returns the timeprecision of the model as an integer. This extension is
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experimental and may be removed without deprecation.
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.. option:: $timeunit
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Returns the timeunit of the current module as an integer. This
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extension is experimental and may be removed without deprecation.
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.. option:: `coverage_block_off
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Specifies the entire begin/end block should be ignored for coverage
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analysis. Must be inside a code block, e.g., within a begin/end pair.
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Same as :option:`coverage_block_off` in :ref:`Configuration Files`.
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.. option:: `systemc_header
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Take the remaining text up to the next :option:`\`verilog` or
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:option:`\`systemc_... <\`systemc_header>` mode switch and place it
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verbatim into the output .h file's header. Must be placed as a module
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item, e.g., directly inside a module/endmodule pair. Despite the name of
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this macro, this also works in pure C++ code.
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.. option:: `systemc_ctor
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Take the remaining text up to the next :option:`\`verilog` or
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:option:`\`systemc_... <\`systemc_header>` mode switch and place it
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verbatim into the C++ class constructor. Must be placed as a module
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item, e.g., directly inside a module/endmodule pair. Despite the name of
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this macro, this also works in pure C++ code.
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.. option:: `systemc_dtor
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Take the remaining text up to the next :option:`\`verilog` or
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:option:`\`systemc_... <\`systemc_header>` mode switch and place it
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verbatim into the C++ class destructor. Must be placed as a module
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item, e.g., directly inside a module/endmodule pair. Despite the name of
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this macro, this also works in pure C++ code.
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.. option:: `systemc_interface
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Take the remaining text up to the next :option:`\`verilog` or
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:option:`\`systemc_... <\`systemc_header>` mode switch and place it
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verbatim into the C++ class interface. Must be placed as a module item,
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e.g., directly inside a module/endmodule pair. Despite the name of this
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macro, this also works in pure C++ code.
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.. option:: `systemc_imp_header
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Take the remaining text up to the next :option:`\`verilog` or
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:option:`\`systemc_... <\`systemc_header>` mode switch and place it
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verbatim into the header of all files for this C++ class implementation.
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Must be placed as a module item, e.g., directly inside a module/endmodule
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pair. Despite the name of this macro, this also works in pure C++ code.
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.. option:: `systemc_implementation
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Take the remaining text up to the next :option:`\`verilog` or
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:option:`\`systemc_... <\`systemc_header>` mode switch and place it
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verbatim into a single file of the C++ class implementation. Must be
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placed as a module item, e.g., directly inside a module/endmodule
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pair. Despite the name of this macro, this also works in pure C++ code.
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If you will be reading or writing any Verilog variables in the C++
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functions, the Verilog signals must be declared with a
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:option:`/*verilator&32;public*/` metacomment. See also the public task
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feature; writing an accessor may result in cleaner code.
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.. option:: `SYSTEMVERILOG
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The SYSTEMVERILOG, SV_COV_START, and related standard defines are set by
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default when :vlopt:`--language <--language>` is "1800-\*".
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.. option:: `VERILATOR
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.. option:: `verilator
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.. option:: `verilator3
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The VERILATOR, verilator and verilator3 defines are set by default so
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you may "\`ifdef" around tool specific constructs.
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.. option:: `verilator_config
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Take the remaining text up to the next :option:`\`verilog` mode switch and
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treat it as Verilator configuration commands. See :ref:`Configuration Files`.
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.. option:: `VERILATOR_TIMING
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The VERILATOR_TIMING define is set when :vlopt:`--timing` is used to
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allow an "\`ifdef" of code dependent on this feature. Note that this define
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is not affected by the :option:`timing_off` configuration file option
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nor timing metacomments.
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.. option:: `verilog
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Switch back to processing Verilog code after a
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:option:`\`systemc_... <\`systemc_header>` mode switch. The Verilog
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code returns to the last language mode specified with
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"\`begin_keywords", or SystemVerilog if none was specified.
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.. option:: /*verilator&32;clock_enable*/
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Deprecated and has no effect (ignored).
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In versions before 5.000:
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Used after a signal declaration to indicate the signal is used to gate a
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clock, and the user is responsible for ensuring there are no races
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related to it. (Typically by adding a latch, and running static timing
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analysis.) For example:
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.. code-block:: sv
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reg enable_r /*verilator clock_enable*/;
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wire gated_clk = clk & enable_r;
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always_ff @(posedge clk)
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enable_r <= enable_early;
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The clock_enable attribute will cause the clock gate to be ignored in
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the scheduling algorithm, sometimes required for correct clock behavior,
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and always improving performance.
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Same as :option:`clock_enable` configuration file option.
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.. option:: /*verilator&32;clocker*/
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.. option:: /*verilator&32;no_clocker*/
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Specifies whether the signal is used as clock or not. See :vlopt:`--clk`.
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Same as :option:`clocker` and :option:`no_clocker` in configuration
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files.
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.. option:: /*verilator&32;coverage_block_off*/
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Specifies the entire begin/end block should be ignored for coverage
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analysis purposes.
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Same as :option:`coverage_block_off` configuration file option.
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.. option:: /*verilator&32;coverage_off*/
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Specifies that that following lines of code should have coverage disabled.
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Often used to ignore an entire module for coverage analysis purposes.
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.. option:: /*verilator&32;coverage_on*/
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Specifies that that following lines of code should have coverage re-enabled
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(if appropriate :vlopt:`--coverage` flags are passed) after being
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disabled earlier with :option:`/*verilator&32;coverage_off*/`.
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.. option:: /*verilator&32;forceable*/
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Specifies that the signal (net or variable) should be made forceable from
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C++ code by generating public `<signame>__VforceEn` and
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`<signame>__VforceVal` signals. The force control signals are created as
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:option:`public_flat` signals.
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To force a marked signal from C++, set the corresponding `__VforceVal`
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variable to the desired value, and the `__VforceEn` signal to the bit-mask
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indicating which bits of the signal to force. To force all bits of the
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target signal, set `__VforceEn` to all ones. To release the signal (or part
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thereof), set appropriate bits of the `__VforceEn` signal to zero.
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Same as :option:`forceable` in configuration files.
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.. _verilator_hier_block:
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.. option:: /*verilator&32;hier_block*/
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Specifies that the module is a unit of hierarchical Verilation. This
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metacomment must be between :code:`module module_name(...);` and
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:code:`endmodule`. The module will not be inlined nor uniquified for
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each instance in hierarchical Verilation. Note that the metacomment is
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ignored unless the :vlopt:`--hierarchical` option is specified.
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See :ref:`Hierarchical Verilation`.
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.. option:: /*verilator&32;inline_module*/
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Specifies the module the comment appears in may be inlined into any
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modules that use this module. This is useful to speed up simulation
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runtime. Note if using :vlopt:`--public` that signals under inlined
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submodules will be named :code:`{submodule}__DOT__{subsignal}` as C++
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does not allow "." in signal names.
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Same as :option:`inline` configuration file option.
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.. option:: /*verilator&32;isolate_assignments*/
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Used after a signal declaration to indicate the assignments to this
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signal in any blocks should be isolated into new blocks. When large
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combinatorial block results in a :option:`UNOPTFLAT` warning, attaching
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this to the signal that was causing a false loop may work around the
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warning.
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IE, with the following:
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.. code-block:: sv
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reg splitme /* verilator isolate_assignments*/;
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// Note the placement of the semicolon above
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always_comb begin
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if (....) begin
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splitme = ....;
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other assignments
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end
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end
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Verilator will internally split the block that assigns to "splitme" into
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two blocks:
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It would then internally break it into (sort of):
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.. code-block:: sv
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// All assignments excluding those to splitme
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always_comb begin
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if (....) begin
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other assignments
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end
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end
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// All assignments to splitme
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always_comb begin
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if (....) begin
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splitme = ....;
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end
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end
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Same as :option:`isolate_assignments` configuration file option.
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.. option:: /*verilator&32;lint_off <msg>*/
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Disable the specified warning message for any warnings following the
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comment.
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.. option:: /*verilator&32;lint_on <msg>*/
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Re-enable the specified warning message for any warnings following the
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comment.
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.. option:: /*verilator&32;lint_restore*/
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After a :code:`/*verilator&32;lint_save*/`, pop the stack containing lint
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message state. Often this is useful at the bottom of include files.
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.. option:: /*verilator&32;lint_save*/
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Push the current state of what lint messages are turned on or off
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to a stack. Later meta-comments may then lint_on or lint_off specific
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messages, then return to the earlier message state by using
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:code:`/*verilator&32;lint_restore*/`. For example:
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.. code-block:: sv
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// verilator lint_save
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// verilator lint_off WIDTH
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... // code needing WIDTH turned off
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// verilator lint_restore
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If WIDTH was on before the lint_off, it would now be restored to on, and
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if it was off before the lint_off it would remain off.
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.. option:: /*verilator&32;no_inline_module*/
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Specifies the module the comment appears in should not be inlined into
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any modules that use this module.
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Same as :option:`no_inline` configuration file option.
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.. option:: /*verilator&32;no_inline_task*/
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Used in a function or task variable definition section to specify the
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function or task should not be inlined into where it is used. This may
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reduce the size of the final executable when a task is used a very large
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number of times. For this flag to work, the task and tasks below it
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must be pure; they cannot reference any variables outside the task
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itself.
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Same as :option:`no_inline` configuration file option.
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.. option:: /*verilator&32;public*/ (on parameter)
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Used after a parameter declaration to indicate the emitted C code should
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have the parameter values visible. Due to C++ language restrictions,
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this may only be used on 64-bit or narrower integral enumerations.
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.. code-block:: sv
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parameter [2:0] PARAM /*verilator public*/ = 2'b0;
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.. option:: /*verilator&32;public*/ (on typedef enum)
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Used after an enum typedef declaration to indicate the emitted C code
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should have the enum values visible. Due to C++ language restrictions,
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this may only be used on 64-bit or narrower integral enumerations.
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.. code-block:: sv
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typedef enum logic [2:0] { ZERO = 3'b0 } pub_t /*verilator public*/;
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.. option:: /*verilator&32;public*/ (on variable)
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Used after an input, output, register, or wire declaration to indicate
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the signal should be declared so that C code may read or write the value
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of the signal. This will also declare this module public; otherwise, use
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:code:`/*verilator&32;public_flat*/`.
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Instead of using public variables, consider making a DPI or public
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function that accesses the variable. This is nicer as it provides an
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obvious entry point compatible across simulators.
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Same as :option:`public` configuration file option.
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.. option:: /*verilator&32;public*/ (on task/function)
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Used inside the declaration section of a function or task declaration to
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indicate the function or task should be made into a C++ function, public
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to outside callers. Public tasks will be declared as a void C++
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function, public functions will get the appropriate non-void (bool,
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uint32_t, etc.) return type. Any input arguments will become C++
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arguments to the function. Any output arguments will become C++
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reference arguments. Any local registers/integers will become function
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automatic variables on the stack.
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Wide variables over 64 bits cannot be function returns, to avoid
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exposing complexities. However, wide variables can be input/outputs;
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they will be passed as references to an array of 32-bit numbers.
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Generally, only the values of stored state (flops) should be written, as
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the model will NOT notice changes made to variables in these functions.
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(Same as when a signal is declared public.)
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You may want to use DPI exports instead, as it's compatible with other
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simulators.
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Same as :option:`public` configuration file option.
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.. option:: /*verilator&32;public_flat*/ (on variable)
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Used after an input, output, register, or wire declaration to indicate
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the signal should be declared so that C code may read or write the value
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of the signal. This will not declare this module public, which means
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the name of the signal or path to it may change based upon the module
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inlining which takes place.
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Same as :option:`public_flat` configuration file option.
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.. option:: /*verilator&32;public_flat_rd*/ (on variable)
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Used after an input, output, register, or wire declaration to indicate
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the signal should be declared public_flat (see above), but read-only.
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Same as :option:`public_flat_rd` configuration file option.
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.. option:: /*verilator&32;public_flat_rw @(<edge_list>)*/ (on variable)
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Used after an input, output, register, or wire declaration to indicate
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the signal should be declared public_flat_rd (see above), and writable,
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where writes should be considered to have the timing specified by the
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given sensitivity edge list. Use of this is implied when using the
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:vlopt:`--public-flat-rw` option.
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Same as :option:`public_flat_rw` configuration file option.
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.. option:: /*verilator&32;public_[|flat|flat_rd|flat_rw]_on [@(<edge_list>)]*/ (as scope)
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Used to wrap multiple signals and parameters with the respective public attribute.
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See attribute above for their respective behavior. Cannot be nested. e.g:
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.. code-block:: sv
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/*verilator public_flat_rw_on*/
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logic clk;
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logic rst;
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parameter width = 8;
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/* verilator public_off*/
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logic data;
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Is equivalent to:
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.. code-block:: sv
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logic clk /*verilator public_flat_rw*/;
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logic rst /*verilator public_flat_rw*/;
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parameter width /*verilator public_flat_rw*/ = 8;
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logic data;
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.. option:: /*verilator&32;public_off*/
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Terminates the previous `/*verilator public*_on*/` directive; see above.
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.. option:: /*verilator&32;public_module*/
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Used after a module statement to indicate the module should not be
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inlined (unless specifically requested) so that C code may access the
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module. Verilator automatically sets this attribute when the module
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contains public signals or \`systemc_ directives. Use of this is
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implied when using the :vlopt:`--public` option.
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Same as :option:`public` configuration file option.
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.. option:: /*verilator&32;sc_clock*/
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Deprecated and ignored. Previously used after an input declaration to
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indicate the signal should be declared in SystemC as a sc_clock instead
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of a bool. This was needed in SystemC 1.1 and 1.2 only; versions 2.0
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and later do not require clock pins to be sc_clocks, and this is no
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longer needed and is ignored.
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.. option:: /*verilator&32;sc_bv*/
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|
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|
Used after a port declaration. It sets the port to be of
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:code:`sc_bv<{width}>` type, instead of bool, uint32_t, or uint64_t.
|
|
This may be useful if the port width is parameterized and the
|
|
instantiating C++ code always wants to have a sc_bv accept any width.
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|
In general, you should avoid using this attribute when unnecessary, as
|
|
the performance decreases significantly with increasing usage of sc_bv.
|
|
|
|
Same as :option:`sc_bv` configuration file option.
|
|
|
|
.. option:: /*verilator&32;sformat*/
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|
|
|
Attached to the final argument of type "input string" of a function or
|
|
task to indicate that the function or task should pass all remaining
|
|
arguments through $sformatf. This allows creation of DPI functions with
|
|
$display-like behavior. See the :file:`test_regress/t/t_dpi_display.v`
|
|
file for an example.
|
|
|
|
Same as :option:`sformat` configuration file option.
|
|
|
|
.. option:: /*verilator&32;split_var*/
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|
|
|
Attached to a variable or a net declaration to break the variable into
|
|
multiple pieces typically to resolve ``UNOPTFLAT`` performance issues.
|
|
Typically the variables to attach this to are recommended by Verilator
|
|
itself; see :option:`UNOPTFLAT`.
|
|
|
|
For example, Verilator will internally convert a variable with the
|
|
metacomment such as:
|
|
|
|
.. code-block:: sv
|
|
|
|
logic [7:0] x [0:1] /*verilator split_var*/;
|
|
|
|
To:
|
|
|
|
.. code-block:: sv
|
|
|
|
logic [7:0] x__BRA__0__KET__ /*verilator split_var*/;
|
|
logic [7:0] x__BRA__1__KET__ /*verilator split_var*/;
|
|
|
|
Note that the generated packed variables retain the split_var
|
|
metacomment because they may be split into smaller pieces according to
|
|
the access patterns.
|
|
|
|
This only supports unpacked arrays, packed arrays, and packed structs of
|
|
integer types (reg, logic, bit, byte, int...); otherwise, if a split was
|
|
requested but cannot occur, a SPLITVAR warning is issued. Splitting
|
|
large arrays may slow down the Verilation speed, so use this only on
|
|
variables that require it.
|
|
|
|
Same as :option:`split_var` configuration file option.
|
|
|
|
.. option:: /*verilator&32;tag <text...>*/
|
|
|
|
Attached after a variable or structure member to indicate opaque (to
|
|
Verilator) text that should be passed through to the XML output as a tag,
|
|
for use by downstream applications.
|
|
|
|
.. option:: /*verilator&32;timing_off*/
|
|
|
|
Ignore all timing constructs after this metacomment. All timing controls
|
|
behave as if they were not there (the same way as with
|
|
:option:`--no-timing`), and :code:`fork`/:code:`join*` blocks are
|
|
converted into :code:`begin`/:code:`end` blocks.
|
|
|
|
Same as :option:`timing_off` configuration file option.
|
|
|
|
.. option:: /*verilator&32;timing_on*/
|
|
|
|
Re-enable all timing constructs after this metacomment (only applicable
|
|
after :option:`timing_off`).
|
|
|
|
Same as :option:`timing_on` configuration file option.
|
|
|
|
.. option:: /*verilator&32;trace_init_task*/
|
|
|
|
Attached to a DPI import to indicate that function should be called when
|
|
initializing tracing. This attribute is indented only to be used
|
|
internally in code that Verilator generates when :vlopt:`--lib-create`
|
|
or :vlopt:`--hierarchical` is used along with :vlopt:`--trace`.
|
|
|
|
.. option:: /*verilator&32;tracing_off*/
|
|
|
|
Disable waveform tracing for all future signals declared in this module,
|
|
or instances below this module. Often this is placed just after a
|
|
primitive's module statement, so that the entire module and instances
|
|
below it are not traced.
|
|
|
|
.. option:: /*verilator&32;tracing_on*/
|
|
|
|
Re-enable waveform tracing for all future signals or instances that are
|
|
declared.
|
|
|
|
.. option:: $stacktrace
|
|
|
|
Called as a task, print a stack trace. Called as a function, return a
|
|
string with a stack trace. This relies on the C++ system trace, which
|
|
may give less meaningful results if the model is not compiled with debug
|
|
symbols. Also, the data represents the C++ stack; the SystemVerilog
|
|
functions/tasks involved may be renamed and/or inlined before becoming
|
|
the C++ functions that may be visible in the stack trace. This
|
|
extension is experimental and may be removed without deprecation.
|