$version Generated by VerilatedVcd $end
$date Thu Aug 25 09:56:30 2022 $end
$timescale 1ps $end

 $scope module top $end
  $scope module t $end
   $var wire  1 # clk $end
   $var wire 32 $ cyc [31:0] $end
   $scope module clkgen $end
    $var wire  1 # clk $end
   $upscope $end
  $upscope $end
 $upscope $end
$enddefinitions $end


#0
0#
b00000000000000000000000000000000 $
#5
1#
b00000000000000000000000000000001 $
#10
0#
#15
1#
b00000000000000000000000000000010 $
#20
0#
#25
1#
b00000000000000000000000000000011 $
#30
0#
#35
1#
b00000000000000000000000000000100 $
#40
0#
#45
1#
b00000000000000000000000000000101 $
#50
0#
#55
1#
b00000000000000000000000000000110 $
#60
0#
#65
1#
b00000000000000000000000000000111 $
#70
0#
#75
1#
b00000000000000000000000000001000 $
#80
0#
#85
1#
b00000000000000000000000000001001 $
#90
0#
#95
1#
b00000000000000000000000000001010 $