%Warning-COMBDLY: t/t_lint_latch_bad_3.v:25:8: Non-blocking assignment '<=' in combinational logic process
                                             : ... This will be executed as a blocking assignment '='!
   25 |     o5 <= 1'b0;  
      |        ^~
                  ... For warning description see https://verilator.org/warn/COMBDLY?v=latest
                  ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message.
                  *** See https://verilator.org/warn/COMBDLY before disabling this,
                  else you may end up with different sim results.
%Warning-COMBDLY: t/t_lint_latch_bad_3.v:37:16: Non-blocking assignment '<=' in combinational logic process
                                              : ... This will be executed as a blocking assignment '='!
   37 |             o5 <= 1'b1;  
      |                ^~
%Warning-COMBDLY: t/t_lint_latch_bad_3.v:42:16: Non-blocking assignment '<=' in combinational logic process
                                              : ... This will be executed as a blocking assignment '='!
   42 |             o5 <=  a;  
      |                ^~
%Warning-COMBDLY: t/t_lint_latch_bad_3.v:63:16: Non-blocking assignment '<=' in combinational logic process
                                              : ... This will be executed as a blocking assignment '='!
   63 |             o5 <= ~b;  
      |                ^~
%Warning-COMBDLY: t/t_lint_latch_bad_3.v:70:12: Non-blocking assignment '<=' in combinational logic process
                                              : ... This will be executed as a blocking assignment '='!
   70 |         o4 <= 1'b0;  
      |            ^~
%Warning-LATCH: t/t_lint_latch_bad_3.v:18:1: Latch inferred for signal 'o5' (not all control paths of combinational always assign a value)
                                           : ... Suggest use of always_latch for intentional latches
   18 | always @(reset or en or a or b)
      | ^~~~~~
%Error: Exiting due to