$date
	Tue Nov  5 20:18:53 2019

$end
$version
	fstWriter
$end
$timescale
	1ns
$end
$scope module top $end
$var wire 1 ! clk $end
$var wire 5 " state $end
$scope module t $end
$var wire 1 ! clk $end
$var int 32 # cyc $end
$var logic 1 $ rstn $end
$var wire 5 " state $end
$var real_parameter 64 % fst_gparam_real $end
$var real_parameter 64 & fst_lparam_real $end
$var real 64 % fst_real $end
$var integer 32 ' fst_integer $end
$var bit 1 ( fst_bit $end
$var logic 1 ) fst_logic $end
$var int 32 * fst_int $end
$var shortint 16 + fst_shortint $end
$var longint 64 , fst_longint $end
$var byte 8 - fst_byte $end
$var parameter 32 . fst_parameter $end
$var parameter 32 / fst_lparam $end
$var supply0 1 0 fst_supply0 $end
$var supply1 1 1 fst_supply1 $end
$var tri0 1 2 fst_tri0 $end
$var tri1 1 3 fst_tri1 $end
$var tri 1 4 fst_tri $end
$var wire 1 5 fst_wire $end
$scope module test $end
$var wire 1 ! clk $end
$var wire 1 $ rstn $end
$var wire 5 " state $end
$var logic 5 6 state_w $end
$var logic 5 7 state_array(0) $end
$var logic 5 8 state_array(1) $end
$var logic 5 9 state_array(2) $end
$scope module unnamedblk2 $end
$var int 32 : i $end
$upscope $end
$scope module unnamedblk1 $end
$var int 32 ; i $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
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1!
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1$
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0!
b10011 "
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1!
b00000000000000000000000000000011 ;
b00000000000000000000000000000010 :
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0!
b11101 "
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1!
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0!
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b00000000000000000000000000000011 ;
b00000000000000000000000000000010 :
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1$
b00000000000000000000000001100011 #
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0!
b01101 "
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1!
b00000000000000000000000001100100 #
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b00000000000000000000000000000010 :
b00000000000000000000000000000011 ;