$version Generated by VerilatedVcd $end
$date Mon Jan 29 09:34:59 2018
 $end
$timescale   1ps $end

 $scope module top $end
  $scope module t $end
   $var wire 32 % c_trace_on [31:0] $end
   $var wire  1 # clk $end
   $var wire 32 $ cyc [31:0] $end
   $var real 64 & r $end
  $upscope $end
 $upscope $end
$enddefinitions $end


#0
0#
b00000000000000000000000000000001 $
b00000000000000000000000000000000 %
r0 &
#10000
1#
b00000000000000000000000000000010 $
r0.1 &
#11000
#12000
#13000
#14000
#15000
0#
#16000
#17000
#18000
#19000
#20000
1#
b00000000000000000000000000000011 $
b00000000000000000000000000000001 %
r0.2 &
#21000
#22000
#23000
#24000
#25000
0#
#26000
#27000
#28000
#29000
#30000
1#
b00000000000000000000000000000100 $
b00000000000000000000000000000010 %
r0.3 &
#31000
#32000
#33000
#34000
#35000
0#
#36000
#37000
#38000
#39000
#40000
1#
b00000000000000000000000000000101 $
b00000000000000000000000000000011 %
r0.4 &
#41000
#42000
#43000
#44000
#45000
0#
#46000
#47000
#48000
#49000
#50000
1#
b00000000000000000000000000000110 $
b00000000000000000000000000000100 %
r0.5 &
#51000
#52000
#53000
#54000
#55000
0#
#56000
#57000
#58000
#59000
#60000
1#
b00000000000000000000000000000111 $
b00000000000000000000000000000101 %
r0.6 &
#61000
#62000
#63000
#64000
#65000
0#
#66000
#67000
#68000
#69000
#70000
1#
b00000000000000000000000000001000 $
b00000000000000000000000000000110 %
r0.7 &
#71000
#72000
#73000
#74000
#75000
0#
#76000
#77000
#78000
#79000
#80000
1#
b00000000000000000000000000001001 $
b00000000000000000000000000000111 %
r0.7999999999999999 &
#81000
#82000
#83000
#84000
#85000
0#
#86000
#87000
#88000
#89000
#90000
1#
b00000000000000000000000000001010 $
b00000000000000000000000000001000 %
r0.8999999999999999 &
#91000
#92000
#93000
#94000
#95000
0#
#96000
#97000
#98000
#99000
#100000
1#
b00000000000000000000000000001011 $
b00000000000000000000000000001001 %
r0.9999999999999999 &
#101000
#102000
#103000
#104000