$version Generated by VerilatedVcd $end $date Thu Oct 24 09:44:07 2019 $end $timescale 1ns $end $scope module top $end $var wire 1 ) clk $end $scope module t $end $var wire 1 ) clk $end $var wire 32 # cyc [31:0] $end $var wire 1 % toggle $end $scope module suba $end $var wire 1 ) clk $end $var wire 32 $ cyc [31:0] $end $var wire 32 & cyc_eq_5_vlCoverageUserTrace [31:0] $end $var wire 1 % toggle $end $upscope $end $scope module subb $end $var wire 1 ) clk $end $var wire 32 $ cyc [31:0] $end $var wire 32 ' cyc_eq_5_vlCoverageUserTrace [31:0] $end $var wire 1 % toggle $end $upscope $end $scope module subc $end $var wire 1 ) clk $end $var wire 32 $ cyc [31:0] $end $var wire 32 ( cyc_eq_5_vlCoverageUserTrace [31:0] $end $var wire 1 % toggle $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000001 # b00000000000000000000000000000001 $ 0% b00000000000000000000000000000000 & b00000000000000000000000000000000 ' b00000000000000000000000000000000 ( 0) #10 b00000000000000000000000000000010 # b00000000000000000000000000000010 $ 1) #15 0) #20 b00000000000000000000000000000011 # b00000000000000000000000000000011 $ 1% 1) #25 0) #30 b00000000000000000000000000000100 # b00000000000000000000000000000100 $ 0% 1) #35 0) #40 b00000000000000000000000000000101 # b00000000000000000000000000000101 $ 1% 1) #45 0) #50 b00000000000000000000000000000110 # b00000000000000000000000000000110 $ 0% b00000000000000000000000000000001 & b00000000000000000000000000000001 ' b00000000000000000000000000000001 ( 1) #55 0) #60 b00000000000000000000000000000111 # b00000000000000000000000000000111 $ 1% 1) #65 0) #70 b00000000000000000000000000001000 # b00000000000000000000000000001000 $ 0% 1) #75 0) #80 b00000000000000000000000000001001 # b00000000000000000000000000001001 $ 1% 1) #85 0) #90 b00000000000000000000000000001010 # b00000000000000000000000000001010 $ 0% 1) #95 0) #100 b00000000000000000000000000001011 # b00000000000000000000000000001011 $ 1% 1)