Wilson Snyder
c6e7d87960
Commentary - Remove author lines as amany contributors now
2012-05-24 19:19:48 -04:00
Wilson Snyder
50edef4ab2
Add Emacs indentation line. No functional change
2012-04-12 21:08:20 -04:00
Wilson Snyder
f13ffe2098
Internals: Merge from VHDL branch. Minor stuff, no functional change.
2012-02-11 20:40:58 -05:00
Wilson Snyder
c2c7c7bd9a
Copyright year update
2012-01-15 10:26:28 -05:00
Wilson Snyder
fb9ca54c95
Fix reporting not found modules if generate-off, bug403.
2011-10-27 20:56:38 -04:00
Wilson Snyder
71c1f00ec2
Copyright year update
2011-01-01 18:21:19 -05:00
Wilson Snyder
f8eabbc100
From Verilog-Perl: Fix parsing single files > 2GB.
2010-04-06 20:20:44 -04:00
Wilson Snyder
6196cf09ff
Add experimental --pipe-filter to filter all Verilog input.
2010-01-20 07:15:51 -05:00
Wilson Snyder
729dfdfed7
Copyright year update
2010-01-05 21:15:06 -05:00
Wilson Snyder
18bebaf5c3
Internals: Add parse-time symbol table for eventual typedef detection
2009-10-31 10:26:53 -04:00
Wilson Snyder
f7efae93d5
Internals: Clean up the main flex/bison files to have some sanity.
...
(Hopefully) no functional change.
. V3Parse.h External consumer interface to V3ParseImp
. V3ParseImp Internals to parser, common to across flex & bison
... V3ParseGrammar Wrapper that includes V3ParseBison
..... V3ParseBison Bison output
... V3ParseLex Wrapper that includes lex output
..... V3Lexer.yy.cpp Flex output
2009-10-31 10:08:38 -04:00
