forked from github/verilator
Tests: Update static test.
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@ -20,7 +20,7 @@ module t (/*AUTOARG*/
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static int st = 2; st++; return st;
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static int st = 2; st++; return st;
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endfunction
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endfunction
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function int f_no_au ();
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function int f_no_au ();
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automatic int st = 2; st++; return st;
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automatic int au = 2; au++; return au;
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endfunction
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endfunction
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function static int f_st_no ();
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function static int f_st_no ();
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@ -30,17 +30,17 @@ module t (/*AUTOARG*/
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static int st = 2; st++; return st;
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static int st = 2; st++; return st;
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endfunction
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endfunction
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function static int f_st_au ();
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function static int f_st_au ();
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automatic int st = 2; st++; return st;
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automatic int au = 2; au++; return au;
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endfunction
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endfunction
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function automatic int f_au_no ();
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function automatic int f_au_no ();
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int st = 2; st++; return st;
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int au = 2; au++; return au;
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endfunction
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endfunction
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function automatic int f_au_st ();
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function automatic int f_au_st ();
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static int st = 2; st++; return st;
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static int st = 2; st++; return st;
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endfunction
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endfunction
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function automatic int f_au_au ();
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function automatic int f_au_au ();
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automatic int st = 2; st++; return st;
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automatic int au = 2; au++; return au;
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endfunction
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endfunction
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initial begin
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initial begin
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@ -88,7 +88,7 @@ module t (/*AUTOARG*/
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else if (cyc == 1) begin
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else if (cyc == 1) begin
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`checkh(ist1, 11);
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`checkh(ist1, 11);
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`checkh(ist2, 21);
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`checkh(ist2, 21);
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`checkh(iau3, 30);
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`checkh(iau3, 0);
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end
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end
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else if (cyc == 5) begin
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else if (cyc == 5) begin
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$write("*-* All Finished *-*\n");
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$write("*-* All Finished *-*\n");
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