forked from github/verilator
Fix error message on missing interface, bug985.
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@ -39,6 +39,8 @@ indicates the contributor was also the author of the fix; Thanks!
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**** Fix crash in commandArgsPlusMatch, bug987. [Jamie Iles]
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**** Fix error message on missing interface, bug985. [Todd Strader]
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* Verilator 3.876 2015-08-12
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@ -372,7 +372,14 @@ public:
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UINFO(9, " insAllIface se"<<(void*)varSymp<<" "<<varp<<endl);
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AstIfaceRefDType* ifacerefp = varp->subDTypep()->castIfaceRefDType();
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if (!ifacerefp) varp->v3fatalSrc("Non-ifacerefs on list!");
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if (!ifacerefp->ifaceViaCellp()) ifacerefp->v3fatalSrc("Unlinked interface");
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if (!ifacerefp->ifaceViaCellp()) {
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if (!ifacerefp->cellp()) { // Probably a NotFoundModule, or a normal module if made mistake
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ifacerefp->v3error("Cannot find file containing interface: "<<AstNode::prettyName(ifacerefp->ifaceName()));
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continue;
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} else {
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ifacerefp->v3fatalSrc("Unlinked interface");
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}
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}
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VSymEnt* ifaceSymp = getNodeSym(ifacerefp->ifaceViaCellp());
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VSymEnt* ifOrPortSymp = ifaceSymp;
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// Link Modport names to the Modport Node under the Interface
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18
test_regress/t/t_interface_missing_bad.pl
Executable file
18
test_regress/t/t_interface_missing_bad.pl
Executable file
@ -0,0 +1,18 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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fails=>1,
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expect=>
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qr{%Error: t/t_interface_missing_bad.v:\d+: Cannot find file containing interface: foo_intf
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.*},
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);
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ok(1);
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1;
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33
test_regress/t/t_interface_missing_bad.v
Normal file
33
test_regress/t/t_interface_missing_bad.v
Normal file
@ -0,0 +1,33 @@
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// DESCRIPTION: Verilator: Missing interface test
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Todd Strader.
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// Interface intentionally not defined
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//interface foo_intf;
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// logic a;
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//endinterface
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module foo_mod
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(
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foo_intf foo
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);
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endmodule
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module t (/*AUTOARG*/);
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foo_intf the_foo ();
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foo_mod
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foo_mod
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(
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.foo (the_foo)
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);
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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