forked from github/verilator
Commentary: Changes update
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@ -19,14 +19,18 @@ Verilator 4.227 devel
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**Minor:**
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* Support IEEE constant signal strengths (#3601). [Ryszard Rozak/Antmicro]
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* Support some IEEE signal strengths (#3601) (#3629). [Ryszard Rozak/Antmicro]
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* Add --main to generate main() C++ (previously was experimental only).
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* Add --build-jobs, and rework arguments for -j (#3623). [Kamil Rakoczy]
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* Rename --bin to --build-dep-bin.
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* Rename debug flags --dumpi-tree, --dumpi-graph, etc. [Geza Lore]
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* Fix thread saftey in SystemC VL_ASSIGN_SBW/WSB (#3494) (#3513). [Mladen Slijepcevic]
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* Fix crash in gate optimization of circular logic (#3543). [Bill Flynn]
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* Fix arguments in non-static method call (#3547) (#3582). [Gustav Svensk]
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* Fix default --mod-prefix when --prefix is repeated (#3603). [Geza Lore]
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* Fix calling trace() after open() segfault (#3610) (#3627). [Yu-Sheng Lin]
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* Fix typedef'ed class conversion to boolean (#3616). [Aleksander Kiryk]
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* Fix Verilation speed when disabled warnings (#3632). [Kamil Rakoczy/Antmicro]
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Verilator 4.226 2022-08-31
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@ -41,6 +45,7 @@ Verilator 4.226 2022-08-31
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* Support $test$plusargs(expr) (#3489).
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* Rename trace rolloverSize() (#3570).
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* Improve Verilation speed with --threads on large designs. [Geza Lore]
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* Improve Verilation memory by reducing V3Number (#3521). [Mariusz Glebocki/Antmicro]
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* Fix struct pattern assignment (#2328) (#3517). [Mostafa Gamal]
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* Fix public combo propagation issues (#2905). [Todd Strader]
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* Fix incorrect tristate logic (#3399) [shareefj, Vighnesh Iyer]
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