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Fix very long VPI signal names (#3929).

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This commit is contained in:
Wilson Snyder 2023-02-02 19:10:23 -05:00
parent 645e1387e0
commit f6d4f1ad02
4 changed files with 14 additions and 3 deletions
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1
Changes
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@ -24,6 +24,7 @@ Verilator 5.007 devel
* Fix real parameters of infinity and NaN. * Fix real parameters of infinity and NaN.
* Fix pattern assignment to unpacked structs (#3510). [Mostafa Garnal] * Fix pattern assignment to unpacked structs (#3510). [Mostafa Garnal]
* Fix single-element replication to dynarray/unpacked/queue (#3548). [Gustav Svensk] * Fix single-element replication to dynarray/unpacked/queue (#3548). [Gustav Svensk]
* Fix very long VPI signal names (#3929). [Marlon James]
Verilator 5.006 2023-01-22 Verilator 5.006 2023-01-22

6
src/V3EmitCSyms.cpp
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@ -235,9 +235,9 @@ class EmitCSyms final : EmitCBaseVisitor {
} }
// UINFO(9, "For " << scopep->name() << " - " << varp->name() << " Scp " // UINFO(9, "For " << scopep->name() << " - " << varp->name() << " Scp "
// << scpName << "Var " << varBase << endl); // << scpName << "Var " << varBase << endl);
const string varBasePretty = AstNode::prettyName(varBase); const string varBasePretty = AstNode::prettyName(VName::dehash(varBase));
const string scpPretty = AstNode::prettyName(scpName); const string scpPretty = AstNode::prettyName(VName::dehash(scpName));
const string scpSym = scopeSymString(scpName); const string scpSym = scopeSymString(VName::dehash(scpName));
// UINFO(9, " scnameins sp " << scpName << " sp " << scpPretty << " ss " // UINFO(9, " scnameins sp " << scpName << " sp " << scpPretty << " ss "
// << scpSym << endl); // << scpSym << endl);
if (v3Global.opt.vpi()) varHierarchyScopes(scpName); if (v3Global.opt.vpi()) varHierarchyScopes(scpName);

9
test_regress/t/t_vpi_var.cpp
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@ -414,6 +414,14 @@ int _mon_check_getput() {
return 0; return 0;
} }
int _mon_check_var_long_name() {
TestVpiHandle vh2 = VPI_HANDLE("LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND");
CHECK_RESULT_NZ(vh2);
const char* p = vpi_get_str(vpiFullName, vh2);
CHECK_RESULT_CSTR(p, "t.LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND");
return 0;
}
int _mon_check_getput_iter() { int _mon_check_getput_iter() {
TestVpiHandle vh2 = VPI_HANDLE("sub"); TestVpiHandle vh2 = VPI_HANDLE("sub");
CHECK_RESULT_NZ(vh2); CHECK_RESULT_NZ(vh2);
@ -699,6 +707,7 @@ extern "C" int mon_check() {
if (int status = _mon_check_value_callbacks()) return status; if (int status = _mon_check_value_callbacks()) return status;
if (int status = _mon_check_var()) return status; if (int status = _mon_check_var()) return status;
if (int status = _mon_check_varlist()) return status; if (int status = _mon_check_varlist()) return status;
if (int status = _mon_check_var_long_name()) return status;
if (int status = _mon_check_getput()) return status; if (int status = _mon_check_getput()) return status;
if (int status = _mon_check_getput_iter()) return status; if (int status = _mon_check_getput_iter()) return status;
if (int status = _mon_check_quad()) return status; if (int status = _mon_check_quad()) return status;

1
test_regress/t/t_vpi_var.v
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@ -28,6 +28,7 @@ extern "C" int mon_check();
reg onebit /*verilator public_flat_rw @(posedge clk) */; reg onebit /*verilator public_flat_rw @(posedge clk) */;
reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */; reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */;
reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */; reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */;
reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND /*verilator public_flat_rw*/;
// verilator lint_off LITENDIAN // verilator lint_off LITENDIAN
reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk) */; reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk) */;