forked from github/verilator
parent
cc45f64280
commit
f68c16a5e6
@ -3362,6 +3362,8 @@ private:
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}
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}
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}
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}
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}
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}
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m_ds.m_dotSymp = m_curSymp;
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iterateChildren(nodep);
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iterateChildren(nodep);
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}
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}
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// V3Width when determines types needs to find enum values and such
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// V3Width when determines types needs to find enum values and such
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17
test_regress/t/t_class_extends_vsyment.pl
Executable file
17
test_regress/t/t_class_extends_vsyment.pl
Executable file
@ -0,0 +1,17 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2020 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt => 1);
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compile(
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);
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ok(1);
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1;
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15
test_regress/t/t_class_extends_vsyment.v
Normal file
15
test_regress/t/t_class_extends_vsyment.v
Normal file
@ -0,0 +1,15 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Foo;
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endclass
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class Bar extends Foo;
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int m_field = get_1();
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function int get_1();
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return 1;
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endfunction
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endclass
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