forked from github/verilator
Fix VPI timed callbacks to be one-shot, pull5.
Signed-off-by: Matthew Ballance <matt.ballance@gmail.com> Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
This commit is contained in:
Matthew Ballance
Wilson Snyder
parent
7a413a121d
commit
f63dfd7028
2
Changes
2
Changes
@ -20,6 +20,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
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**** Fix hang on concat error, bug1608. [Bogdan Vukobratovic]
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**** Fix VPI timed callbacks to be one-shot, pull5. [Matthew Ballance]
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* Verilator 4.022 2019-11-10
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@ -416,7 +416,9 @@ public:
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for (VpioTimedCbs::iterator it=s_s.m_timedCbs.begin(); it!=s_s.m_timedCbs.end(); ) {
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if (VL_UNLIKELY(it->first <= time)) {
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VerilatedVpioCb* vop = it->second;
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++it; // iterator may be deleted by callback
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VpioTimedCbs::iterator last_it = it;
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++it; // Timed callbacks are one-shot
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s_s.m_timedCbs.erase(last_it);
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VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: timed_callback %p\n", vop););
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(vop->cb_rtnp()) (vop->cb_datap());
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}
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256
test_regress/t/t_vpi_time_cb.cpp
Normal file
256
test_regress/t/t_vpi_time_cb.cpp
Normal file
@ -0,0 +1,256 @@
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// -*- mode: C++; c-file-style: "cc-mode" -*-
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//*************************************************************************
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//
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// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License.
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// Version 2.0.
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//
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// Verilator is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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//*************************************************************************
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#ifdef IS_VPI
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#include "vpi_user.h"
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#else
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#include "Vt_vpi_time_cb.h"
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#include "verilated.h"
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#include "svdpi.h"
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#include <dlfcn.h>
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#include "Vt_vpi_time_cb__Dpi.h"
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#include "verilated_vpi.h"
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#include "verilated_vcd_c.h"
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#endif
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#include <cstdlib>
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#include <cstdio>
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#include <cstring>
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#include <iostream>
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using namespace std;
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#include "TestSimulator.h"
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#include "TestVpi.h"
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// __FILE__ is too long
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#define FILENM "t_vpi_time_cb.cpp"
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#define TEST_MSG \
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if (0) printf
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unsigned int main_time = false;
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unsigned int callback_count_time1 = 3;
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unsigned int callback_count_time2 = 4;
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unsigned int callback_count_start_of_sim = 0;
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//======================================================================
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#define CHECK_RESULT_VH(got, exp) \
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if ((got) != (exp)) { \
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printf("%%Error: %s:%d: GOT = %p EXP = %p\n", FILENM, __LINE__, (got), (exp)); \
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return __LINE__; \
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}
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#define CHECK_RESULT_NZ(got) \
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if (!(got)) { \
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printf("%%Error: %s:%d: GOT = NULL EXP = !NULL\n", FILENM, __LINE__); \
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return __LINE__; \
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}
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// Use cout to avoid issues with %d/%lx etc
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#define CHECK_RESULT(got, exp) \
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if ((got) != (exp)) { \
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cout << dec << "%Error: " << FILENM << ":" << __LINE__ << ": GOT = " << (got) \
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<< " EXP = " << (exp) << endl; \
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return __LINE__; \
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}
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#define CHECK_RESULT_HEX(got, exp) \
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if ((got) != (exp)) { \
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cout << dec << "%Error: " << FILENM << ":" << __LINE__ << hex << ": GOT = " << (got) \
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<< " EXP = " << (exp) << endl; \
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return __LINE__; \
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}
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#define CHECK_RESULT_CSTR(got, exp) \
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if (strcmp((got), (exp))) { \
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printf("%%Error: %s:%d: GOT = '%s' EXP = '%s'\n", FILENM, __LINE__, \
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(got) ? (got) : "<null>", (exp) ? (exp) : "<null>"); \
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return __LINE__; \
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}
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#define CHECK_RESULT_CSTR_STRIP(got, exp) CHECK_RESULT_CSTR(got + strspn(got, " "), exp)
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#define STRINGIFY(x) STRINGIFY2(x)
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#define STRINGIFY2(x) #x
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//======================================================================
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#ifdef IS_VPI
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static int _time_cb1(p_cb_data cb_data) {
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s_vpi_time t;
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t.type = vpiSimTime;
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vpi_get_time(0, &t);
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// fprintf(stdout, "time_cb1: %d\n", t.low);
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CHECK_RESULT(callback_count_time1, t.low);
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callback_count_time1++;
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t_cb_data cb_data_n;
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cb_data_n.reason = cbAfterDelay;
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t.type = vpiSimTime;
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t.high = 0;
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t.low = 1;
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cb_data_n.time = &t;
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cb_data_n.cb_rtn = _time_cb1;
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vpi_register_cb(&cb_data_n);
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return 0;
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}
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static int _time_cb2(p_cb_data cb_data) {
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s_vpi_time t;
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t.type = vpiSimTime;
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vpi_get_time(0, &t);
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// fprintf(stdout, "time_cb2: %d\n", t.low);
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CHECK_RESULT(callback_count_time2, t.low);
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callback_count_time2++;
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t_cb_data cb_data_n;
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cb_data_n.reason = cbAfterDelay;
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t.type = vpiSimTime;
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t.high = 0;
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t.low = 1;
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cb_data_n.time = &t;
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cb_data_n.cb_rtn = _time_cb2;
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vpi_register_cb(&cb_data_n);
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return 0;
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}
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static int _start_of_sim_cb(p_cb_data cb_data) {
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t_cb_data cb_data_n1, cb_data_n2;
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s_vpi_time t1, t2;
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cb_data_n1.reason = cbAfterDelay;
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t1.type = vpiSimTime;
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t1.high = 0;
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t1.low = 3;
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cb_data_n1.time = &t1;
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cb_data_n1.cb_rtn = _time_cb1;
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vpi_register_cb(&cb_data_n1);
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cb_data_n2.reason = cbAfterDelay;
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t2.type = vpiSimTime;
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t2.high = 0;
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t2.low = 4;
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cb_data_n2.time = &t2;
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cb_data_n2.cb_rtn = _time_cb2;
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vpi_register_cb(&cb_data_n2);
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callback_count_start_of_sim++;
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return 0;
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}
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static int _end_of_sim_cb(p_cb_data cb_data) {
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CHECK_RESULT(callback_count_start_of_sim, 1);
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fprintf(stdout, "*-* All Finished *-*\n");
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return 0;
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}
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// cver entry
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#ifdef __cplusplus
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extern "C"
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#endif
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void vpi_compat_bootstrap(void) {
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t_cb_data cb_data;
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// VL_PRINTF("register start-of-sim callback\n");
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cb_data.reason = cbStartOfSimulation;
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cb_data.time = 0;
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cb_data.cb_rtn = _start_of_sim_cb;
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vpi_register_cb(&cb_data);
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cb_data.reason = cbEndOfSimulation;
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cb_data.time = 0;
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cb_data.cb_rtn = _end_of_sim_cb;
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vpi_register_cb(&cb_data);
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}
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// icarus entry
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void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
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#else
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double sc_time_stamp() { return main_time; }
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int main(int argc, char** argv, char** env) {
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double sim_time = 1100;
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Verilated::commandArgs(argc, argv);
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Verilated::debug(0);
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VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out
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#ifdef VERILATOR
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# ifdef TEST_VERBOSE
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Verilated::scopesDump();
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# endif
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#endif
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#if VM_TRACE
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Verilated::traceEverOn(true);
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VL_PRINTF("Enabling waves...\n");
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VerilatedVcdC* tfp = new VerilatedVcdC;
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topp->trace(tfp, 99);
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tfp->open(STRINGIFY(TEST_OBJ_DIR) "/simx.vcd");
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#endif
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// Load and initialize the PLI application
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{
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void* lib = dlopen("./obj_vlt/t_vpi_time_cb/libvpi.so", RTLD_LAZY);
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void* bootstrap = dlsym(lib, "vpi_compat_bootstrap");
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((void (*)(void))bootstrap)();
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}
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VerilatedVpi::callCbs(cbStartOfSimulation);
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topp->eval();
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topp->clk = 0;
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main_time += 1;
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while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
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main_time += 1;
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topp->eval();
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VerilatedVpi::callValueCbs();
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VerilatedVpi::callTimedCbs();
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topp->clk = !topp->clk;
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// mon_do();
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#if VM_TRACE
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if (tfp) tfp->dump(main_time);
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#endif
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}
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VerilatedVpi::callCbs(cbEndOfSimulation);
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if (!Verilated::gotFinish()) {
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vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish");
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}
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topp->final();
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#if VM_TRACE
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if (tfp) tfp->close();
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#endif
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delete topp; VL_DANGLING(topp);
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exit(0L);
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}
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#endif
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30
test_regress/t/t_vpi_time_cb.pl
Executable file
30
test_regress/t/t_vpi_time_cb.pl
Executable file
@ -0,0 +1,30 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2010 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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scenarios(simulator => 1, iv => 1);
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compile(
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make_top_shell => 0,
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make_main => 0,
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make_pli => 1,
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sim_time => 2100,
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iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -Diverilog"],
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v_flags2 => ["+define+USE_VPI_NOT_DPI"],
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verilator_flags2 => ["-CFLAGS '-DVL_DEBUG -ggdb' --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_time_cb.cpp -LDFLAGS '-ldl -rdynamic'"],
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);
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execute(
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iv_pli => 1,
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ms_pli => 1,
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check_finished => 1,
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all_run_flags => ['+PLUS +INT=1234 +STRSTR']
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);
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ok(1);
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1;
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116
test_regress/t/t_vpi_time_cb.v
Normal file
116
test_regress/t/t_vpi_time_cb.v
Normal file
@ -0,0 +1,116 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2010 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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module t (/*AUTOARG*/
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// Inputs
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input clk
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);
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`ifndef VERILATOR
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reg clk_r = 0;
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always #10 clk_r = ~clk_r;
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assign clk = clk_r;
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`endif
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reg onebit /*verilator public_flat_rw @(posedge clk) */;
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reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */;
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reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */;
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reg [61:0] quads[3:2] /*verilator public_flat_rw @(posedge clk) */;
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reg [31:0] count /*verilator public_flat_rd */;
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reg [31:0] half_count /*verilator public_flat_rd */;
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reg [7:0] text_byte /*verilator public_flat_rw @(posedge clk) */;
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reg [15:0] text_half /*verilator public_flat_rw @(posedge clk) */;
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reg [31:0] text_word /*verilator public_flat_rw @(posedge clk) */;
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reg [63:0] text_long /*verilator public_flat_rw @(posedge clk) */;
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reg [511:0] text /*verilator public_flat_rw @(posedge clk) */;
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integer status;
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sub sub();
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// Test loop
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initial begin
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count = 0;
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onebit = 1'b0;
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fourthreetwoone[3] = 0; // stop icarus optimizing away
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text_byte = "B";
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text_half = "Hf";
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text_word = "Word";
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text_long = "Long64b";
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text = "Verilog Test module";
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/*
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if (status!=0) begin
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$write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
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$stop;
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end
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$write("%%Info: Checking results\n");
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if (onebit != 1'b1) $stop;
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if (quads[2] != 62'h12819213_abd31a1c) $stop;
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if (quads[3] != 62'h1c77bb9b_3784ea09) $stop;
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if (text_byte != "A") $stop;
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if (text_half != "T2") $stop;
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if (text_word != "Tree") $stop;
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if (text_long != "44Four44") $stop;
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if (text != "lorem ipsum") $stop;
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*/
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end
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always @(posedge clk) begin
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count <= count + 2;
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if (count[1])
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half_count <= half_count + 2;
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if (count == 1000) begin
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// $write("*-* All Finished *-*\n");
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$finish;
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end
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end
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genvar i;
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generate
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for (i=1; i<=128; i=i+1) begin : arr
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arr #(.LENGTH(i)) arr();
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end
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endgenerate
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endmodule : t
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module sub;
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reg subsig1 /*verilator public_flat_rd*/;
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reg subsig2 /*verilator public_flat_rd*/;
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`ifdef iverilog
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// stop icarus optimizing signals away
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wire redundant = subsig1 | subsig2;
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`endif
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endmodule : sub
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module arr;
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parameter LENGTH = 1;
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reg [LENGTH-1:0] sig /*verilator public_flat_rw*/;
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reg [LENGTH-1:0] rfr /*verilator public_flat_rw*/;
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reg check /*verilator public_flat_rw*/;
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reg verbose /*verilator public_flat_rw*/;
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initial begin
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sig = {LENGTH{1'b0}};
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rfr = {LENGTH{1'b0}};
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end
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always @(posedge check) begin
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if (verbose) $display("%m : %x %x", sig, rfr);
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if (check && sig != rfr) $stop;
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check <= 0;
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end
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endmodule : arr
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212
test_regress/t/t_vpi_zero_time_cb.cpp
Normal file
212
test_regress/t/t_vpi_zero_time_cb.cpp
Normal file
@ -0,0 +1,212 @@
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// -*- mode: C++; c-file-style: "cc-mode" -*-
|
||||
//*************************************************************************
|
||||
//
|
||||
// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can
|
||||
// redistribute it and/or modify it under the terms of either the GNU
|
||||
// Lesser General Public License Version 3 or the Perl Artistic License.
|
||||
// Version 2.0.
|
||||
//
|
||||
// Verilator is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
//*************************************************************************
|
||||
|
||||
#ifdef IS_VPI
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||||
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#include "vpi_user.h"
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||||
#else
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||||
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||||
#include "Vt_vpi_zero_time_cb.h"
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#include "verilated.h"
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#include "svdpi.h"
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#include <dlfcn.h>
|
||||
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#include "Vt_vpi_zero_time_cb__Dpi.h"
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#include "verilated_vpi.h"
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#include "verilated_vcd_c.h"
|
||||
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#endif
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|
||||
#include <cstdlib>
|
||||
#include <cstdio>
|
||||
#include <cstring>
|
||||
#include <iostream>
|
||||
using namespace std;
|
||||
|
||||
#include "TestSimulator.h"
|
||||
#include "TestVpi.h"
|
||||
|
||||
// __FILE__ is too long
|
||||
#define FILENM "t_vpi_zero_time_cb.cpp"
|
||||
|
||||
#define TEST_MSG \
|
||||
if (0) printf
|
||||
|
||||
unsigned int main_time = false;
|
||||
unsigned int callback_count_zero_time = 0;
|
||||
unsigned int callback_count_start_of_sim = 0;
|
||||
|
||||
//======================================================================
|
||||
|
||||
#define CHECK_RESULT_VH(got, exp) \
|
||||
if ((got) != (exp)) { \
|
||||
printf("%%Error: %s:%d: GOT = %p EXP = %p\n", FILENM, __LINE__, (got), (exp)); \
|
||||
return __LINE__; \
|
||||
}
|
||||
|
||||
#define CHECK_RESULT_NZ(got) \
|
||||
if (!(got)) { \
|
||||
printf("%%Error: %s:%d: GOT = NULL EXP = !NULL\n", FILENM, __LINE__); \
|
||||
return __LINE__; \
|
||||
}
|
||||
|
||||
// Use cout to avoid issues with %d/%lx etc
|
||||
#define CHECK_RESULT(got, exp) \
|
||||
if ((got) != (exp)) { \
|
||||
cout << dec << "%Error: " << FILENM << ":" << __LINE__ << ": GOT = " << (got) \
|
||||
<< " EXP = " << (exp) << endl; \
|
||||
return __LINE__; \
|
||||
}
|
||||
|
||||
#define CHECK_RESULT_HEX(got, exp) \
|
||||
if ((got) != (exp)) { \
|
||||
cout << dec << "%Error: " << FILENM << ":" << __LINE__ << hex << ": GOT = " << (got) \
|
||||
<< " EXP = " << (exp) << endl; \
|
||||
return __LINE__; \
|
||||
}
|
||||
|
||||
#define CHECK_RESULT_CSTR(got, exp) \
|
||||
if (strcmp((got), (exp))) { \
|
||||
printf("%%Error: %s:%d: GOT = '%s' EXP = '%s'\n", FILENM, __LINE__, \
|
||||
(got) ? (got) : "<null>", (exp) ? (exp) : "<null>"); \
|
||||
return __LINE__; \
|
||||
}
|
||||
|
||||
#define CHECK_RESULT_CSTR_STRIP(got, exp) CHECK_RESULT_CSTR(got + strspn(got, " "), exp)
|
||||
|
||||
#define STRINGIFY(x) STRINGIFY2(x)
|
||||
#define STRINGIFY2(x) #x
|
||||
|
||||
//======================================================================
|
||||
|
||||
#ifdef IS_VPI
|
||||
|
||||
static int _zero_time_cb(p_cb_data cb_data) {
|
||||
callback_count_zero_time++;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _start_of_sim_cb(p_cb_data cb_data) {
|
||||
t_cb_data cb_data_n;
|
||||
s_vpi_time t;
|
||||
|
||||
cb_data_n.reason = cbAfterDelay;
|
||||
t.type = vpiSimTime;
|
||||
t.high = 0;
|
||||
t.low = 0;
|
||||
cb_data_n.time = &t;
|
||||
cb_data_n.cb_rtn = _zero_time_cb;
|
||||
vpi_register_cb(&cb_data_n);
|
||||
callback_count_start_of_sim++;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _end_of_sim_cb(p_cb_data cb_data) {
|
||||
CHECK_RESULT(callback_count_start_of_sim, 1);
|
||||
CHECK_RESULT(callback_count_zero_time, 1);
|
||||
fprintf(stdout, "*-* All Finished *-*\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
// cver entry
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
#endif
|
||||
|
||||
void vpi_compat_bootstrap(void) {
|
||||
t_cb_data cb_data;
|
||||
|
||||
// VL_PRINTF("register start-of-sim callback\n");
|
||||
cb_data.reason = cbStartOfSimulation;
|
||||
cb_data.time = 0;
|
||||
cb_data.cb_rtn = _start_of_sim_cb;
|
||||
vpi_register_cb(&cb_data);
|
||||
|
||||
cb_data.reason = cbEndOfSimulation;
|
||||
cb_data.time = 0;
|
||||
cb_data.cb_rtn = _end_of_sim_cb;
|
||||
vpi_register_cb(&cb_data);
|
||||
}
|
||||
|
||||
// icarus entry
|
||||
void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
|
||||
|
||||
#else
|
||||
|
||||
double sc_time_stamp() { return main_time; }
|
||||
int main(int argc, char** argv, char** env) {
|
||||
double sim_time = 1100;
|
||||
Verilated::commandArgs(argc, argv);
|
||||
Verilated::debug(0);
|
||||
|
||||
VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out
|
||||
|
||||
#ifdef VERILATOR
|
||||
#ifdef TEST_VERBOSE
|
||||
Verilated::scopesDump();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if VM_TRACE
|
||||
Verilated::traceEverOn(true);
|
||||
VL_PRINTF("Enabling waves...\n");
|
||||
VerilatedVcdC* tfp = new VerilatedVcdC;
|
||||
topp->trace(tfp, 99);
|
||||
tfp->open(STRINGIFY(TEST_OBJ_DIR) "/simx.vcd");
|
||||
#endif
|
||||
|
||||
// Load and initialize the PLI application
|
||||
{
|
||||
void* lib = dlopen("./obj_vlt/t_vpi_zero_time_cb/libvpi.so", RTLD_LAZY);
|
||||
void* bootstrap = dlsym(lib, "vpi_compat_bootstrap");
|
||||
((void (*)(void))bootstrap)();
|
||||
}
|
||||
|
||||
VerilatedVpi::callCbs(cbStartOfSimulation);
|
||||
|
||||
topp->eval();
|
||||
topp->clk = 0;
|
||||
main_time += 10;
|
||||
|
||||
while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
|
||||
main_time += 1;
|
||||
topp->eval();
|
||||
VerilatedVpi::callValueCbs();
|
||||
VerilatedVpi::callTimedCbs();
|
||||
topp->clk = !topp->clk;
|
||||
// mon_do();
|
||||
#if VM_TRACE
|
||||
if (tfp) tfp->dump(main_time);
|
||||
#endif
|
||||
}
|
||||
|
||||
VerilatedVpi::callCbs(cbEndOfSimulation);
|
||||
|
||||
if (!Verilated::gotFinish()) {
|
||||
vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish");
|
||||
}
|
||||
topp->final();
|
||||
|
||||
#if VM_TRACE
|
||||
if (tfp) tfp->close();
|
||||
#endif
|
||||
|
||||
delete topp; VL_DANGLING(topp);
|
||||
exit(0L);
|
||||
}
|
||||
|
||||
#endif
|
||||
30
test_regress/t/t_vpi_zero_time_cb.pl
Executable file
30
test_regress/t/t_vpi_zero_time_cb.pl
Executable file
@ -0,0 +1,30 @@
|
||||
#!/usr/bin/perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2010 by Wilson Snyder. This program is free software; you can
|
||||
# redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
|
||||
scenarios(simulator => 1, iv => 1);
|
||||
|
||||
compile(
|
||||
make_top_shell => 0,
|
||||
make_main => 0,
|
||||
make_pli => 1,
|
||||
sim_time => 2100,
|
||||
iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -Diverilog"],
|
||||
v_flags2 => ["+define+USE_VPI_NOT_DPI"],
|
||||
verilator_flags2 => ["-CFLAGS '-DVL_DEBUG -ggdb' --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_zero_time_cb.cpp -LDFLAGS '-ldl -rdynamic'"],
|
||||
);
|
||||
|
||||
execute(
|
||||
iv_pli => 1,
|
||||
ms_pli => 1,
|
||||
check_finished => 1,
|
||||
all_run_flags => ['+PLUS +INT=1234 +STRSTR']
|
||||
);
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
116
test_regress/t/t_vpi_zero_time_cb.v
Normal file
116
test_regress/t/t_vpi_zero_time_cb.v
Normal file
@ -0,0 +1,116 @@
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// Copyright 2010 by Wilson Snyder. This program is free software; you can
|
||||
// redistribute it and/or modify it under the terms of either the GNU
|
||||
// Lesser General Public License Version 3 or the Perl Artistic License
|
||||
// Version 2.0.
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
input clk
|
||||
);
|
||||
|
||||
`ifndef VERILATOR
|
||||
reg clk_r = 0;
|
||||
always #10 clk_r = ~clk_r;
|
||||
assign clk = clk_r;
|
||||
`endif
|
||||
|
||||
reg onebit /*verilator public_flat_rw @(posedge clk) */;
|
||||
reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */;
|
||||
reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */;
|
||||
|
||||
reg [61:0] quads[3:2] /*verilator public_flat_rw @(posedge clk) */;
|
||||
|
||||
reg [31:0] count /*verilator public_flat_rd */;
|
||||
reg [31:0] half_count /*verilator public_flat_rd */;
|
||||
|
||||
reg [7:0] text_byte /*verilator public_flat_rw @(posedge clk) */;
|
||||
reg [15:0] text_half /*verilator public_flat_rw @(posedge clk) */;
|
||||
reg [31:0] text_word /*verilator public_flat_rw @(posedge clk) */;
|
||||
reg [63:0] text_long /*verilator public_flat_rw @(posedge clk) */;
|
||||
reg [511:0] text /*verilator public_flat_rw @(posedge clk) */;
|
||||
|
||||
integer status;
|
||||
|
||||
sub sub();
|
||||
|
||||
// Test loop
|
||||
initial begin
|
||||
count = 0;
|
||||
onebit = 1'b0;
|
||||
fourthreetwoone[3] = 0; // stop icarus optimizing away
|
||||
text_byte = "B";
|
||||
text_half = "Hf";
|
||||
text_word = "Word";
|
||||
text_long = "Long64b";
|
||||
text = "Verilog Test module";
|
||||
|
||||
/*
|
||||
if (status!=0) begin
|
||||
$write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
|
||||
$stop;
|
||||
end
|
||||
$write("%%Info: Checking results\n");
|
||||
if (onebit != 1'b1) $stop;
|
||||
if (quads[2] != 62'h12819213_abd31a1c) $stop;
|
||||
if (quads[3] != 62'h1c77bb9b_3784ea09) $stop;
|
||||
if (text_byte != "A") $stop;
|
||||
if (text_half != "T2") $stop;
|
||||
if (text_word != "Tree") $stop;
|
||||
if (text_long != "44Four44") $stop;
|
||||
if (text != "lorem ipsum") $stop;
|
||||
*/
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
count <= count + 2;
|
||||
if (count[1])
|
||||
half_count <= half_count + 2;
|
||||
|
||||
if (count == 1000) begin
|
||||
// $write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i=1; i<=128; i=i+1) begin : arr
|
||||
arr #(.LENGTH(i)) arr();
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule : t
|
||||
|
||||
module sub;
|
||||
reg subsig1 /*verilator public_flat_rd*/;
|
||||
reg subsig2 /*verilator public_flat_rd*/;
|
||||
`ifdef iverilog
|
||||
// stop icarus optimizing signals away
|
||||
wire redundant = subsig1 | subsig2;
|
||||
`endif
|
||||
endmodule : sub
|
||||
|
||||
module arr;
|
||||
|
||||
parameter LENGTH = 1;
|
||||
|
||||
reg [LENGTH-1:0] sig /*verilator public_flat_rw*/;
|
||||
reg [LENGTH-1:0] rfr /*verilator public_flat_rw*/;
|
||||
|
||||
reg check /*verilator public_flat_rw*/;
|
||||
reg verbose /*verilator public_flat_rw*/;
|
||||
|
||||
initial begin
|
||||
sig = {LENGTH{1'b0}};
|
||||
rfr = {LENGTH{1'b0}};
|
||||
end
|
||||
|
||||
always @(posedge check) begin
|
||||
if (verbose) $display("%m : %x %x", sig, rfr);
|
||||
if (check && sig != rfr) $stop;
|
||||
check <= 0;
|
||||
end
|
||||
|
||||
endmodule : arr
|
||||
Loading…
Reference in New Issue
Block a user