Tests: Add bug508, bug509 examples

This commit is contained in:
Wilson Snyder 2012-05-08 17:41:42 -04:00
parent e498b73933
commit f5ace0f72a
4 changed files with 86 additions and 0 deletions

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#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
v_flags2 => ["--lint-only"],
fails=>1,
expect=>
'%Error: t/t_bitsel_const_bad.v:\d+: Illegal bit or array select; variable already selected, or bad dimension: b
.*
%Error: Exiting due to.*',
);
ok(1);
1;

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// DESCRIPTION: Verilator: Test of select from constant
//
// This tests issue 508, bit select of constant fails
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jeremy Bennett.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Note that if we declare "wire [0:0] b", this works just fine.
wire a;
wire b;
assign b = 1'b0;
assign a = b[0]; // IEEE illegal can't extract scalar
endmodule

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#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# Comple time only test
compile (
verilator_flags2 => ["--lint-only"],
fails=>1,
# expect=>
# TBD better error message, bug509
#'.*
#%Error: Exiting due to.*',
);
ok(1);
1;

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// DESCRIPTION: Verilator: Test of select from constant
//
// This tests issue 509, bit select of constant fails
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jeremy Bennett.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// a and b are arrays of length 1.
wire a[0:0]; // Array of nets
wire b[0:0];
assign a = 1'b0; // Only net assignment allowed
assign b = a[0]; // Only net assignment allowed
endmodule