forked from github/verilator
Tests: Add bug508, bug509 examples
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test_regress/t/t_bitsel_const_bad.pl
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test_regress/t/t_bitsel_const_bad.pl
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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v_flags2 => ["--lint-only"],
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fails=>1,
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expect=>
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'%Error: t/t_bitsel_const_bad.v:\d+: Illegal bit or array select; variable already selected, or bad dimension: b
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.*
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%Error: Exiting due to.*',
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);
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ok(1);
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1;
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test_regress/t/t_bitsel_const_bad.v
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test_regress/t/t_bitsel_const_bad.v
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// DESCRIPTION: Verilator: Test of select from constant
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//
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// This tests issue 508, bit select of constant fails
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Jeremy Bennett.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// Note that if we declare "wire [0:0] b", this works just fine.
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wire a;
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wire b;
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assign b = 1'b0;
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assign a = b[0]; // IEEE illegal can't extract scalar
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endmodule
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test_regress/t/t_bitsel_wire_array_bad.pl
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test_regress/t/t_bitsel_wire_array_bad.pl
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# Comple time only test
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compile (
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verilator_flags2 => ["--lint-only"],
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fails=>1,
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# expect=>
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# TBD better error message, bug509
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#'.*
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#%Error: Exiting due to.*',
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);
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ok(1);
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1;
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test_regress/t/t_bitsel_wire_array_bad.v
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test_regress/t/t_bitsel_wire_array_bad.v
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// DESCRIPTION: Verilator: Test of select from constant
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//
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// This tests issue 509, bit select of constant fails
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Jeremy Bennett.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// a and b are arrays of length 1.
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wire a[0:0]; // Array of nets
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wire b[0:0];
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assign a = 1'b0; // Only net assignment allowed
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assign b = a[0]; // Only net assignment allowed
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endmodule
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