Mario1159/verilator
1
0
Fork 0
forked from github/verilator
Code Pull Requests Releases 1 Activity

Add data types to --xml.

Browse Source
This commit is contained in:
Wilson Snyder 2017-11-08 21:27:15 -05:00
parent cbb7cd16d0
commit f555c93c11
3 changed files with 36 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Changes
View File

@ -8,6 +8,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
**** Detect MSB overflow when under VL_DEBUG, bug1238. [Junyi Xi]
**** Add data types to --xml. [Rui Terra]
* Verilator 3.914 2017-10-14

59
src/V3EmitXml.cpp
View File

@ -37,8 +37,13 @@
// Emit statements and math operators
class EmitXmlFileVisitor : public AstNVisitor {
// NODE STATE
//Entire netlist:
// AstNode::user1 -> uint64_t, number to connect crossrefs
// MEMBERS
V3OutFile* m_ofp;
uint64_t m_id;
// METHODS
static int debug() {
@ -64,11 +69,21 @@ class EmitXmlFileVisitor : public AstNVisitor {
}
// XML methods
void outputId(AstNode* nodep) {
if (!nodep->user1()) { nodep->user1(++m_id); }
puts("\""+cvtToStr(nodep->user1())+"\"");
}
void outputTag(AstNode* nodep, string tag) {
if (tag=="") tag = VString::downcase(nodep->typeName());
puts("<"+tag+" "+nodep->fileline()->xml());
if (nodep->castNodeDType()) { puts(" id="); outputId(nodep); }
if (nodep->name()!="") { puts(" name="); putsQuoted(nodep->prettyName()); }
if (nodep->tag()!="") { puts(" tag="); putsQuoted(nodep->tag()); }
if (AstNodeDType* dtp = nodep->castNodeDType()) {
if (dtp->skipRefp() && dtp->skipRefp()!=dtp) { puts(" sub_dtype_id="); outputId(dtp->skipRefp()); }
} else {
if (nodep->dtypep()) { puts(" dtype_id="); outputId(nodep->dtypep()); }
}
}
void outputChildrenEnd(AstNode* nodep, string tag) {
if (tag=="") tag = VString::downcase(nodep->typeName());
@ -111,13 +126,13 @@ class EmitXmlFileVisitor : public AstNVisitor {
outputChildrenEnd(nodep, "port");
}
virtual void visit(AstAssignW* nodep) {
outputTag(nodep, "contAssign"); // IEEE: vpiContAssign
outputTag(nodep, "contassign"); // IEEE: vpiContAssign
outputChildrenEnd(nodep, "contAssign");
}
// Data types
virtual void visit(AstBasicDType* nodep) {
outputTag(nodep, "basicDType ");
outputTag(nodep, "basicdtype ");
if (nodep->isRanged()) {
puts(" left=\""+cvtToStr(nodep->left())+"\"");
puts(" right=\""+cvtToStr(nodep->right())+"\"");
@ -133,50 +148,12 @@ class EmitXmlFileVisitor : public AstNVisitor {
public:
EmitXmlFileVisitor(AstNode* nodep, V3OutFile* ofp) {
m_ofp = ofp;
m_id = 0;
nodep->accept(*this);
}
virtual ~EmitXmlFileVisitor() {}
};
//######################################################################
// Emit to a stream (perhaps stringstream)
class EmitXmlPrefixedFormatter : public V3OutFormatter {
ostream& m_os;
string m_prefix; // What to print at beginning of each line
int m_flWidth; // Padding of fileline
int m_column; // Rough location; need just zero or non-zero
FileLine* m_prefixFl;
// METHODS
virtual void putcOutput(char chr) {
if (chr == '\n') {
m_column = 0;
m_os<<chr;
} else {
if (m_column == 0) {
m_column = 10;
m_os<<m_prefixFl->ascii()+":";
m_os<<V3OutFile::indentSpaces(m_flWidth-(m_prefixFl->ascii().length()+1));
m_os<<" ";
m_os<<m_prefix;
}
m_column++;
m_os<<chr;
}
}
public:
void prefixFl(FileLine* fl) { m_prefixFl = fl; }
FileLine* prefixFl() const { return m_prefixFl; }
int column() const { return m_column; }
EmitXmlPrefixedFormatter(ostream& os, const string& prefix, int flWidth)
: V3OutFormatter("__STREAM", V3OutFormatter::LA_VERILOG)
, m_os(os), m_prefix(prefix), m_flWidth(flWidth) {
m_column = 0;
m_prefixFl = v3Global.rootp()->fileline(); // NETLIST's fileline instead of NULL to avoid NULL checks
}
virtual ~EmitXmlPrefixedFormatter() {}
};
//######################################################################
// EmitXml class functions

32
test_regress/t/t_xml_tag.out
View File

@ -10,25 +10,25 @@
</files>
<netlist>
<module fl="e6" name="m">
<var fl="e8" name="clk_ip" tag="clk_ip"/>
<var fl="e9" name="rst_ip"/>
<var fl="e10" name="foo_op" tag="foo_op"/>
<typedef fl="e14" name="my_struct"/>
<var fl="e23" name="this_struct"/>
<var fl="e8" name="clk_ip" tag="clk_ip" dtype_id="1"/>
<var fl="e9" name="rst_ip" dtype_id="1"/>
<var fl="e10" name="foo_op" tag="foo_op" dtype_id="1"/>
<typedef fl="e14" name="my_struct" dtype_id="2"/>
<var fl="e23" name="this_struct" dtype_id="3"/>
</module>
<typetable fl="a0">
<basicDType fl="e8" name="logic"/>
<structdtype fl="e14">
<memberdtype fl="e15" name="clk" tag="this is clk"/>
<memberdtype fl="e16" name="k"/>
<memberdtype fl="e17" name="enable" tag="enable"/>
<memberdtype fl="e18" name="data" tag="data"/>
<basicdtype fl="e8" id="1" name="logic"/>
<structdtype fl="e14" id="2">
<memberdtype fl="e15" id="4" name="clk" tag="this is clk" sub_dtype_id="5"/>
<memberdtype fl="e16" id="6" name="k" sub_dtype_id="7"/>
<memberdtype fl="e17" id="8" name="enable" tag="enable" sub_dtype_id="9"/>
<memberdtype fl="e18" id="10" name="data" tag="data" sub_dtype_id="11"/>
</structdtype>
<basicDType fl="e15" name="logic"/>
<basicDType fl="e16" name="logic"/>
<basicDType fl="e17" name="logic"/>
<basicDType fl="e18" name="logic"/>
<refdtype fl="e23" name="my_struct"/>
<basicdtype fl="e15" id="5" name="logic"/>
<basicdtype fl="e16" id="7" name="logic"/>
<basicdtype fl="e17" id="9" name="logic"/>
<basicdtype fl="e18" id="11" name="logic"/>
<refdtype fl="e23" id="3" name="my_struct" sub_dtype_id="2"/>
</typetable>
</netlist>
</verilator_xml>