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Tests: Prove fixed (#2410)

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This commit is contained in:
Wilson Snyder 2022-10-16 10:36:18 -04:00
parent 76ccd332a6
commit f3292a3651
2 changed files with 32 additions and 15 deletions
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9
test_regress/t/t_delay.v
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@ -17,11 +17,15 @@ module t (/*AUTOARG*/
reg [31:0] dly0;
wire [31:0] dly1;
wire [31:0] dly2 = dly1 + 32'h1;
wire [31:0] dly3;
typedef struct packed { int dly; } dly_s_t;
dly_s_t dly_s;
assign #(1.2000000000000000) dly1 = dly0 + 32'h1;
assign #(sub.delay) dly3 = dly1 + 1;
sub sub();
always @ (posedge clk) begin
cyc <= cyc + 1;
@ -41,9 +45,14 @@ module t (/*AUTOARG*/
//dly0 <= # dly_s.dly 32'h55; // Unsupported, issue-2410
end
else if (cyc == 99) begin
if (dly3 !== 32'h57) $stop;
$write("*-* All Finished *-*\n");
#100 $finish;
end
end
endmodule
module sub;
realtime delay = 2.3;
endmodule

36
test_regress/t/t_delay_stmtdly_bad.out
View File

@ -1,31 +1,39 @@
%Warning-ASSIGNDLY: t/t_delay.v:24:11: Ignoring timing control on this assignment/primitive due to --no-timing
%Warning-ASSIGNDLY: t/t_delay.v:25:11: Ignoring timing control on this assignment/primitive due to --no-timing
: ... In instance t
24 | assign #(1.2000000000000000) dly1 = dly0 + 32'h1;
25 | assign #(1.2000000000000000) dly1 = dly0 + 32'h1;
| ^
... For warning description see https://verilator.org/warn/ASSIGNDLY?v=latest
... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message.
%Warning-ASSIGNDLY: t/t_delay.v:29:18: Ignoring timing control on this assignment/primitive due to --no-timing
%Warning-ASSIGNDLY: t/t_delay.v:26:11: Ignoring timing control on this assignment/primitive due to --no-timing
: ... In instance t
29 | dly0 <= #0 32'h11;
26 | assign #(sub.delay) dly3 = dly1 + 1;
| ^
%Warning-ASSIGNDLY: t/t_delay.v:32:18: Ignoring timing control on this assignment/primitive due to --no-timing
%Warning-ASSIGNDLY: t/t_delay.v:33:18: Ignoring timing control on this assignment/primitive due to --no-timing
: ... In instance t
32 | dly0 <= #0.12 dly0 + 32'h12;
33 | dly0 <= #0 32'h11;
| ^
%Warning-ASSIGNDLY: t/t_delay.v:40:18: Ignoring timing control on this assignment/primitive due to --no-timing
%Warning-ASSIGNDLY: t/t_delay.v:36:18: Ignoring timing control on this assignment/primitive due to --no-timing
: ... In instance t
40 | dly0 <= #(dly_s.dly) 32'h55;
36 | dly0 <= #0.12 dly0 + 32'h12;
| ^
%Warning-STMTDLY: t/t_delay.v:45:10: Ignoring delay on this statement due to --no-timing
%Warning-ASSIGNDLY: t/t_delay.v:44:18: Ignoring timing control on this assignment/primitive due to --no-timing
: ... In instance t
45 | #100 $finish;
44 | dly0 <= #(dly_s.dly) 32'h55;
| ^
%Warning-UNUSED: t/t_delay.v:22:12: Signal is not used: 'dly_s'
%Warning-STMTDLY: t/t_delay.v:50:10: Ignoring delay on this statement due to --no-timing
: ... In instance t
22 | dly_s_t dly_s;
50 | #100 $finish;
| ^
%Warning-UNUSED: t/t_delay.v:23:12: Signal is not used: 'dly_s'
: ... In instance t
23 | dly_s_t dly_s;
| ^~~~~
%Warning-BLKSEQ: t/t_delay.v:39:20: Blocking assignment '=' in sequential logic process
%Warning-UNUSED: t/t_delay.v:57:13: Signal is not used: 'delay'
: ... In instance t.sub
57 | realtime delay = 2.3;
| ^~~~~
%Warning-BLKSEQ: t/t_delay.v:43:20: Blocking assignment '=' in sequential logic process
: ... Suggest using delayed assignment '<='
39 | dly_s.dly = 55;
43 | dly_s.dly = 55;
| ^
%Error: Exiting due to