From f1874b211fa8268a7fbc3838860ad6b27f34024a Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 3 Oct 2015 07:12:56 -0400 Subject: [PATCH] Support , bug977. --- Changes | 2 ++ src/V3AstNodes.h | 2 ++ src/verilog.l | 1 + src/verilog.y | 3 ++- test_regress/t/t_sys_sformat.v | 6 ++++++ 5 files changed, 13 insertions(+), 1 deletion(-) diff --git a/Changes b/Changes index 128bdffe6..418720645 100644 --- a/Changes +++ b/Changes @@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks! ** Add --vpi flag, and fix VPI linkage, bug969. [Arthur Kahlich] +** Support $sformatf, bug977. [Johan Bjork] + **** Add VerilatedScopeNameMap for introspection, bug966. [Todd Strader] **** Fix very long module names, bug937. [Todd Strader] diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index 22a1dc3c7..3864abb21 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -2208,11 +2208,13 @@ class AstSFormatF : public AstNode { public: AstSFormatF(FileLine* fl, const string& text, bool hidden, AstNode* exprsp) : AstNode(fl), m_text(text), m_hidden(hidden) { + dtypeSetString(); addNOp1p(exprsp); addNOp2p(NULL); } ASTNODE_NODE_FUNCS(SFormatF, SFORMATF) virtual string name() const { return m_text; } virtual int instrCount() const { return instrCountPli(); } virtual V3Hash sameHash() const { return V3Hash(text()); } + virtual bool hasDType() const { return true; } virtual bool same(AstNode* samep) const { return text()==samep->castSFormatF()->text(); } virtual string verilogKwd() const { return "$sformatf"; } void exprsp(AstNode* nodep) { addOp1p(nodep); } // op1 = Expressions to output diff --git a/src/verilog.l b/src/verilog.l index c683152e1..a188f3858 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -221,6 +221,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "$setup" { FL; return yaTIMINGSPEC; } "$setuphold" { FL; return yaTIMINGSPEC; } "$sformat" { FL; return yD_SFORMAT; } + "$sformatf" { FL; return yD_SFORMATF; } "$skew" { FL; return yaTIMINGSPEC; } "$sqrt" { FL; return yD_SQRT; } "$sscanf" { FL; return yD_SSCANF; } diff --git a/src/verilog.y b/src/verilog.y index fb3beeeac..0cea2b9ca 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -474,6 +474,7 @@ class AstSenTree; %token yD_RIGHT "$right" %token yD_RTOI "$rtoi" %token yD_SFORMAT "$sformat" +%token yD_SFORMATF "$sformatf" %token yD_SIGNED "$signed" %token yD_SIZE "$size" %token yD_SQRT "$sqrt" @@ -2655,7 +2656,7 @@ system_f_call: // IEEE: system_tf_call (as func) | yD_RIGHT '(' expr ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_RIGHT,$3,NULL); } | yD_RIGHT '(' expr ',' expr ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_RIGHT,$3,$5); } | yD_RTOI '(' expr ')' { $$ = new AstRToIS($1,$3); } - //| yD_SFORMATF '(' str commaEListE ')' { $$ = new AstSFormatF($1,*$3,false,$4); } // Have AST, just need testing and debug + | yD_SFORMATF '(' str commaEListE ')' { $$ = new AstSFormatF($1,*$3,false,$4); } | yD_SIGNED '(' expr ')' { $$ = new AstSigned($1,$3); } | yD_SIZE '(' expr ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_SIZE,$3,NULL); } | yD_SIZE '(' expr ',' expr ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_SIZE,$3,$5); } diff --git a/test_regress/t/t_sys_sformat.v b/test_regress/t/t_sys_sformat.v index fbda9b957..ff2a6d172 100644 --- a/test_regress/t/t_sys_sformat.v +++ b/test_regress/t/t_sys_sformat.v @@ -16,6 +16,8 @@ module t; reg [8:1] char; reg [48*8:1] str; reg [48*8:1] str2; + string str3; + real r; @@ -32,6 +34,10 @@ module t; `ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif if (str2 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop; + str3 = $sformatf("n=%b q=%d w=%s", n, q, wide); +`ifdef TEST_VERBOSE $display("str3=%0s",str3); `endif + if (str3 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop; + $swrite(str2, "e=%e", r); $swrite(str2, "e=%f", r); $swrite(str2, "e=%g", r);