From f083805ab5facdcb4e3bf4853eac4d3866c30a9b Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 6 Jun 2020 10:06:32 -0400
Subject: [PATCH] Support --bbox-unsup parsing of parameterized classes

---
 src/verilog.y                           | 16 +++++++++++--
 test_regress/t/t_class_vparam_unsup.out | 10 ++++++++
 test_regress/t/t_class_vparam_unsup.pl  | 19 +++++++++++++++
 test_regress/t/t_class_vparam_unsup.v   | 32 +++++++++++++++++++++++++
 4 files changed, 75 insertions(+), 2 deletions(-)
 create mode 100644 test_regress/t/t_class_vparam_unsup.out
 create mode 100755 test_regress/t/t_class_vparam_unsup.pl
 create mode 100644 test_regress/t/t_class_vparam_unsup.v

diff --git a/src/verilog.y b/src/verilog.y
index a1740a5a1..7d184e7da 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -29,6 +29,7 @@
 
 #include <cstdlib>
 #include <cstdarg>
+#include <stack>
 
 #define YYERROR_VERBOSE 1
 #define YYINITDEPTH 10000  // Older bisons ignore YYMAXDEPTH
@@ -67,12 +68,14 @@ public:
     AstNodeDType* m_memDTypep;  // Pointer to data type for next member declaration
     AstNodeModule* m_modp;  // Last module for timeunits
     bool m_pinAnsi;  // In ANSI port list
-    int m_pinNum;  // Pin number currently parsing
     FileLine* m_instModuleFl;  // Fileline of module referenced for instantiations
     string m_instModule;  // Name of module referenced for instantiations
     AstPin* m_instParamp;  // Parameters for instantiations
     bool m_tracingParse;  // Tracing disable for parser
 
+    int m_pinNum;  // Pin number currently parsing
+    std::stack<int> m_pinStack;  // Queue of pin numbers being parsed
+
     static int s_modTypeImpNum;  // Implicit type number, incremented each module
 
     // CONSTRUCTORS
@@ -141,6 +144,15 @@ public:
         if (m_varDTypep) VL_DO_CLEAR(m_varDTypep->deleteTree(), m_varDTypep = NULL);
         m_varDTypep = dtypep;
     }
+    void pinPush() {
+        m_pinStack.push(m_pinNum);
+        m_pinNum = 1;
+    }
+    void pinPop(FileLine* fl) {
+        if (VL_UNCOVERABLE(m_pinStack.empty())) { fl->v3fatalSrc("Underflow of pin stack"); }
+        m_pinNum = m_pinStack.top();
+        m_pinStack.pop();
+    }
     AstPackage* unitPackage(FileLine* fl) {
         // Find one made earlier?
         VSymEnt* symp = SYMP->symRootp()->findIdFlat(AstPackage::dollarUnitName());
@@ -2667,7 +2679,7 @@ instRange<rangep>:
 	;
 
 cellparamList<pinp>:
-		{VARRESET_LIST(UNKNOWN);} cellparamItList	{ $$ = $2; VARRESET_NONLIST(UNKNOWN); }
+		{ GRAMMARP->pinPush(); } cellparamItList	{ $$ = $2; GRAMMARP->pinPop(CRELINE()); }
 	;
 
 cellpinList<pinp>:
diff --git a/test_regress/t/t_class_vparam_unsup.out b/test_regress/t/t_class_vparam_unsup.out
new file mode 100644
index 000000000..9025acc4b
--- /dev/null
+++ b/test_regress/t/t_class_vparam_unsup.out
@@ -0,0 +1,10 @@
+%Error: t/t_class_vparam_unsup.v:12:1: Unsupported: virtual classes
+   12 | virtual class vclass #(type CTYPE_t = arg_class_t);
+      | ^~~~~~~
+%Error: t/t_class_vparam_unsup.v:13:58: Unsupported: Parameter classes
+   13 |    pure virtual function void funcname(paramed_class_t #(CTYPE_t) v);
+      |                                                          ^~~~~~~
+%Error: t/t_class_vparam_unsup.v:13:4: Unsupported: pure virtual class method
+   13 |    pure virtual function void funcname(paramed_class_t #(CTYPE_t) v);
+      |    ^~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_class_vparam_unsup.pl b/test_regress/t/t_class_vparam_unsup.pl
new file mode 100755
index 000000000..ce380f717
--- /dev/null
+++ b/test_regress/t/t_class_vparam_unsup.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+lint(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_class_vparam_unsup.v b/test_regress/t/t_class_vparam_unsup.v
new file mode 100644
index 000000000..d19d0988e
--- /dev/null
+++ b/test_regress/t/t_class_vparam_unsup.v
@@ -0,0 +1,32 @@
+// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
+//
+// Simple bi-directional alias test.
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+typedef class paramed_class_t;
+typedef class arg_class_t;
+
+virtual class vclass #(type CTYPE_t = arg_class_t);
+   pure virtual function void funcname(paramed_class_t #(CTYPE_t) v);
+endclass
+
+class paramed_class_t #(type TYPE=int);
+endclass
+
+class arg_class_t;
+endclass
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   always @ (posedge clk) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule