From ef87d057fc04d60d4aa11d52816ad23f55ef4796 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 7 Mar 2022 17:43:33 -0500 Subject: [PATCH] Fix $fscanf etc to return -1 on EOF (#3113). --- Changes | 1 + include/verilated.cpp | 2 +- include/verilated_imp.h | 4 ++-- test_regress/t/t_sys_file_basic.pl | 1 - test_regress/t/t_sys_file_eof.pl | 21 ++++++++++++++++++ test_regress/t/t_sys_file_eof.v | 34 ++++++++++++++++++++++++++++++ 6 files changed, 59 insertions(+), 4 deletions(-) create mode 100755 test_regress/t/t_sys_file_eof.pl create mode 100644 test_regress/t/t_sys_file_eof.v diff --git a/Changes b/Changes index 38edaa32e..bfaceed21 100644 --- a/Changes +++ b/Changes @@ -20,6 +20,7 @@ Verilator 4.219 devel * Fix skipping public enum values with four-state values (#3303). * Fix $readmem file not found to be warning not error (#3310). [Alexander Grobman] * Fix class stringification on wide arrays (#3312). [Iru Cai] +* Fix $fscanf etc to return -1 on EOF (#3113). [Jose Tejada] * Fix public function arguments that are arrayed (#3316). [pawel256] * Fix unnamedblk error on foreach (#3321). [Aliaksei Chapyzhenka] * Fix crash in recursive module inlining (#3324). [Larry Doolittle] diff --git a/include/verilated.cpp b/include/verilated.cpp index e90644bfa..4401ffb45 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -1497,7 +1497,7 @@ void VL_FWRITEF(IData fpi, const char* formatp, ...) VL_MT_SAFE { IData VL_FSCANF_IX(IData fpi, const char* formatp, ...) VL_MT_SAFE { // While threadsafe, each thread can only access different file handles FILE* const fp = VL_CVT_I_FP(fpi); - if (VL_UNLIKELY(!fp)) return 0; + if (VL_UNLIKELY(!fp)) return ~0U; // -1 va_list ap; va_start(ap, formatp); diff --git a/include/verilated_imp.h b/include/verilated_imp.h index b14876fac..7f07587db 100644 --- a/include/verilated_imp.h +++ b/include/verilated_imp.h @@ -316,14 +316,14 @@ public: // But only for verilated*.cpp IData fdSeek(IData fdi, IData offset, IData origin) VL_MT_SAFE_EXCLUDES(m_fdMutex) { const VerilatedLockGuard lock{m_fdMutex}; const VerilatedFpList fdlist = fdToFpList(fdi); - if (VL_UNLIKELY(fdlist.size() != 1)) return 0; + if (VL_UNLIKELY(fdlist.size() != 1)) return ~0U; // -1 return static_cast( std::fseek(*fdlist.begin(), static_cast(offset), static_cast(origin))); } IData fdTell(IData fdi) VL_MT_SAFE_EXCLUDES(m_fdMutex) { const VerilatedLockGuard lock{m_fdMutex}; const VerilatedFpList fdlist = fdToFpList(fdi); - if (VL_UNLIKELY(fdlist.size() != 1)) return 0; + if (VL_UNLIKELY(fdlist.size() != 1)) return ~0U; // -1 return static_cast(std::ftell(*fdlist.begin())); } void fdWrite(IData fdi, const std::string& output) VL_MT_SAFE_EXCLUDES(m_fdMutex) { diff --git a/test_regress/t/t_sys_file_basic.pl b/test_regress/t/t_sys_file_basic.pl index 7b4870947..fe1cedbce 100755 --- a/test_regress/t/t_sys_file_basic.pl +++ b/test_regress/t/t_sys_file_basic.pl @@ -13,7 +13,6 @@ scenarios(simulator => 1); unlink("$Self->{obj_dir}/t_sys_file_basic_test.log"); compile( - v_flags2 => ['+incdir+../include'], # Build without cached objects, see bug363 make_flags => 'VM_PARALLEL_BUILDS=0', ); diff --git a/test_regress/t/t_sys_file_eof.pl b/test_regress/t/t_sys_file_eof.pl new file mode 100755 index 000000000..b46d46042 --- /dev/null +++ b/test_regress/t/t_sys_file_eof.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_sys_file_eof.v b/test_regress/t/t_sys_file_eof.v new file mode 100644 index 000000000..8b8069a4f --- /dev/null +++ b/test_regress/t/t_sys_file_eof.v @@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`include "verilated.v" + +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +module t; + + integer f; + integer i; + integer j; + + initial begin + f = $fopen("/does-not-exist", "r"); + `checkd(f, 0); + i = $fscanf(f, "check %d", j); + `checkd(i, -1); + i = $fgetc(f); + `checkd(i, -1); + i = $ftell(f); + `checkd(i, -1); + i = $rewind(f); + `checkd(i, -1); + i = $fseek(f, 0, 0); + `checkd(i, -1); + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule