From ede7236945d3e84e3b51b621a277e285daa2b76f Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 6 Dec 2018 07:12:39 -0500
Subject: [PATCH] For --xml, add additional var information, bug1372.

---
 Changes                        |  2 ++
 src/V3AstNodes.cpp             |  2 ++
 src/V3EmitXml.cpp              | 12 +++++++++++-
 test_regress/t/t_xml_first.out | 20 ++++++++++----------
 test_regress/t/t_xml_tag.out   |  8 ++++----
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/Changes b/Changes
index de058e7a7..cd6d50ee7 100644
--- a/Changes
+++ b/Changes
@@ -5,6 +5,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 * Verilator 4.009 devel
 
+****  For --xml, add additional var information, bug1372. [Jonathan Kimmitt]
+
 
 * Verilator 4.008 2018-12-01
 
diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp
index d5899664a..d12a643df 100644
--- a/src/V3AstNodes.cpp
+++ b/src/V3AstNodes.cpp
@@ -200,6 +200,8 @@ string AstVar::verilogKwd() const {
         return "wire";
     } else if (varType()==AstVarType::WREAL) {
         return "wreal";
+    } else if (varType()==AstVarType::IFACEREF) {
+        return "ifaceref";
     } else {
         return dtypep()->name();
     }
diff --git a/src/V3EmitXml.cpp b/src/V3EmitXml.cpp
index 863ee8e06..15eaa88d0 100644
--- a/src/V3EmitXml.cpp
+++ b/src/V3EmitXml.cpp
@@ -115,7 +115,17 @@ class EmitXmlFileVisitor : public AstNVisitor {
 	outputChildrenEnd(nodep, "");
     }
     virtual void visit(AstVar* nodep) {
-	outputTag(nodep, "");
+        AstVarType typ = nodep->varType();
+        string kw = nodep->verilogKwd();
+        string vt = nodep->dtypep()->name();
+        outputTag(nodep, "");
+        if (nodep->isIO()) {
+            puts(" dir="); putsQuoted(kw);
+            puts(" vartype="); putsQuoted(!vt.empty()
+					  ? vt : typ == AstVarType::PORT ? "port" : "unknown");
+        } else {
+            puts(" vartype="); putsQuoted(!vt.empty() ? vt : kw);
+        }
 	puts(" origName="); putsQuoted(nodep->origName());
 	outputChildrenEnd(nodep, "");
     }
diff --git a/test_regress/t/t_xml_first.out b/test_regress/t/t_xml_first.out
index 1f4b543ae..e6743605d 100644
--- a/test_regress/t/t_xml_first.out
+++ b/test_regress/t/t_xml_first.out
@@ -20,10 +20,10 @@
   </cells>
   <netlist>
     <module fl="f6" name="t" origName="t" topModule="1">
-      <var fl="f12" name="clk" dtype_id="1" origName="clk"/>
-      <var fl="f13" name="d" dtype_id="2" origName="d"/>
-      <var fl="f14" name="q" dtype_id="2" origName="q"/>
-      <var fl="f16" name="between" dtype_id="2" origName="between"/>
+      <var fl="f12" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
+      <var fl="f13" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
+      <var fl="f14" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
+      <var fl="f16" name="between" dtype_id="2" vartype="logic" origName="between"/>
       <instance fl="f18" name="cell1" defName="mod1" origName="cell1">
         <port fl="f18" name="q" direction="out" portIndex="1">
           <varref fl="f18" name="between" dtype_id="2"/>
@@ -48,9 +48,9 @@
       </instance>
     </module>
     <module fl="f33" name="mod1" origName="mod1">
-      <var fl="f35" name="clk" dtype_id="1" origName="clk"/>
-      <var fl="f36" name="d" dtype_id="2" origName="d"/>
-      <var fl="f37" name="q" dtype_id="2" origName="q"/>
+      <var fl="f35" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
+      <var fl="f36" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
+      <var fl="f37" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
       <always fl="f39">
         <sentree fl="f39">
           <senitem fl="f39" edgeType="POS">
@@ -64,9 +64,9 @@
       </always>
     </module>
     <module fl="f44" name="mod2" origName="mod2">
-      <var fl="f46" name="clk" dtype_id="1" origName="clk"/>
-      <var fl="f47" name="d" dtype_id="2" origName="d"/>
-      <var fl="f48" name="q" dtype_id="2" origName="q"/>
+      <var fl="f46" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
+      <var fl="f47" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
+      <var fl="f48" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
       <contassign fl="f51" dtype_id="2">
         <varref fl="f51" name="d" dtype_id="2"/>
         <varref fl="f51" name="q" dtype_id="2"/>
diff --git a/test_regress/t/t_xml_tag.out b/test_regress/t/t_xml_tag.out
index aed866106..43ace0dbb 100644
--- a/test_regress/t/t_xml_tag.out
+++ b/test_regress/t/t_xml_tag.out
@@ -17,11 +17,11 @@
   </cells>
   <netlist>
     <module fl="f6" name="m" origName="m">
-      <var fl="f8" name="clk_ip" tag="clk_ip" dtype_id="1" origName="clk_ip"/>
-      <var fl="f9" name="rst_ip" dtype_id="1" origName="rst_ip"/>
-      <var fl="f10" name="foo_op" tag="foo_op" dtype_id="1" origName="foo_op"/>
+      <var fl="f8" name="clk_ip" tag="clk_ip" dtype_id="1" dir="input" vartype="logic" origName="clk_ip"/>
+      <var fl="f9" name="rst_ip" dtype_id="1" dir="input" vartype="logic" origName="rst_ip"/>
+      <var fl="f10" name="foo_op" tag="foo_op" dtype_id="1" dir="output" vartype="logic" origName="foo_op"/>
       <typedef fl="f14" name="my_struct" tag="my_struct" dtype_id="2"/>
-      <var fl="f23" name="this_struct" tag="this_struct" dtype_id="3" origName="this_struct"/>
+      <var fl="f23" name="this_struct" tag="this_struct" dtype_id="3" vartype="" origName="this_struct"/>
     </module>
     <typetable fl="a0">
       <basicdtype  fl="f23" id="4" name="logic" left="31" right="0"/>