forked from github/verilator
Throw warning if static variable is declared in a loop (#4018)
Signed-off-by: Ryszard Rozak <rrozak@antmicro.com>
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@ -65,6 +65,7 @@ private:
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int m_genblkAbove = 0; // Begin block number of if/case/for above
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int m_genblkAbove = 0; // Begin block number of if/case/for above
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int m_genblkNum = 0; // Begin block number, 0=none seen
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int m_genblkNum = 0; // Begin block number, 0=none seen
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VLifetime m_lifetime = VLifetime::STATIC; // Propagating lifetime
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VLifetime m_lifetime = VLifetime::STATIC; // Propagating lifetime
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bool m_insideLoop = false; // True if the node is inside a loop
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// METHODS
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// METHODS
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void cleanFileline(AstNode* nodep) {
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void cleanFileline(AstNode* nodep) {
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@ -222,6 +223,9 @@ private:
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void visit(AstVar* nodep) override {
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void visit(AstVar* nodep) override {
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cleanFileline(nodep);
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cleanFileline(nodep);
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if (nodep->lifetime().isStatic() && m_insideLoop) {
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nodep->v3warn(E_UNSUPPORTED, "Unsupported: Static variable inside a loop");
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}
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if (nodep->lifetime().isNone() && nodep->varType() != VVarType::PORT) {
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if (nodep->lifetime().isNone() && nodep->varType() != VVarType::PORT) {
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nodep->lifetime(m_lifetime);
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nodep->lifetime(m_lifetime);
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}
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}
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@ -459,6 +463,8 @@ private:
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// 2. ASTSELBIT(first, var0))
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// 2. ASTSELBIT(first, var0))
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// 3. ASTSELLOOPVARS(first, var0..var1))
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// 3. ASTSELLOOPVARS(first, var0..var1))
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// 4. DOT(DOT(first, second), ASTSELBIT(third, var0))
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// 4. DOT(DOT(first, second), ASTSELBIT(third, var0))
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VL_RESTORER(m_insideLoop);
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m_insideLoop = true;
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AstNode* bracketp = nodep->arrayp();
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AstNode* bracketp = nodep->arrayp();
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while (AstDot* dotp = VN_CAST(bracketp, Dot)) bracketp = dotp->rhsp();
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while (AstDot* dotp = VN_CAST(bracketp, Dot)) bracketp = dotp->rhsp();
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if (AstSelBit* const selp = VN_CAST(bracketp, SelBit)) {
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if (AstSelBit* const selp = VN_CAST(bracketp, SelBit)) {
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@ -471,14 +477,34 @@ private:
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} else if (VN_IS(bracketp, SelLoopVars)) {
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} else if (VN_IS(bracketp, SelLoopVars)) {
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// Ok
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// Ok
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} else {
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} else {
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nodep->v3error(
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nodep->v3error("Syntax error; foreach missing bracketed loop variable (IEEE "
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"Syntax error; foreach missing bracketed loop variable (IEEE 1800-2017 12.7.3)");
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"1800-2017 12.7.3)");
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VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
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VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
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return;
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return;
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}
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}
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iterateChildren(nodep);
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iterateChildren(nodep);
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}
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}
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void visit(AstRepeat* nodep) override {
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VL_RESTORER(m_insideLoop);
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{
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m_insideLoop = true;
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iterateChildren(nodep);
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}
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}
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void visit(AstDoWhile* nodep) override {
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VL_RESTORER(m_insideLoop);
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{
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m_insideLoop = true;
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iterateChildren(nodep);
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}
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}
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void visit(AstWhile* nodep) override {
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VL_RESTORER(m_insideLoop);
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{
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m_insideLoop = true;
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iterateChildren(nodep);
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}
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}
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void visit(AstNodeModule* nodep) override {
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void visit(AstNodeModule* nodep) override {
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V3Config::applyModule(nodep);
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V3Config::applyModule(nodep);
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5
test_regress/t/t_static_in_loop_unsup.out
Normal file
5
test_regress/t/t_static_in_loop_unsup.out
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@ -0,0 +1,5 @@
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%Error-UNSUPPORTED: t/t_static_in_loop_unsup.v:14:24: Unsupported: Static variable inside a loop
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14 | static int a = 0;
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| ^
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error: Exiting due to
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19
test_regress/t/t_static_in_loop_unsup.pl
Executable file
19
test_regress/t/t_static_in_loop_unsup.pl
Executable file
@ -0,0 +1,19 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt => 1);
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lint(
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fails => 1,
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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26
test_regress/t/t_static_in_loop_unsup.v
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26
test_regress/t/t_static_in_loop_unsup.v
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@ -0,0 +1,26 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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initial begin
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int x = 0;
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while (x < 10) begin : outer_loop
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int y = 0;
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while (y < x) begin : inner_loop
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static int a = 0;
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a++;
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y++;
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end
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x++;
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end
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if (outer_loop.inner_loop.a != 45) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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