From ebeb645539a6b2f3f87c6d9999a46f83de2022b3 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 30 Mar 2020 20:09:55 -0400
Subject: [PATCH] Commentary

---
 src/verilog.y              | 1 +
 test_regress/t/t_typedef.v | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/src/verilog.y b/src/verilog.y
index 14ac2ec20..49fc199c1 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1664,6 +1664,7 @@ member_decl_assignment<memberp>:	// Derived from IEEE: variable_decl_assignment
                           }
 	|	id variable_dimensionListE '=' variable_declExpr
 			{ $4->v3error("Unsupported: Initial values in struct/union members.");
+			  // But still need error if packed according to IEEE 7.2.2
 			  $$ = NULL; }
 	|	idSVKwd					{ $$ = NULL; }
 	//
diff --git a/test_regress/t/t_typedef.v b/test_regress/t/t_typedef.v
index 7b8150134..78f966825 100644
--- a/test_regress/t/t_typedef.v
+++ b/test_regress/t/t_typedef.v
@@ -7,6 +7,8 @@
 program t;
    parameter SIZE = 5;
 
+   typedef vec_t;  // Forward
+
    typedef reg [SIZE-1:0] vec_t ;
    vec_t a; initial a =0;