Fix error instead of warning on large concat, msg1768.

This commit is contained in:
Wilson Snyder 2015-12-08 21:25:43 -05:00
parent f920b3945e
commit ebad6cde36
6 changed files with 74 additions and 1 deletions

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@ -29,6 +29,8 @@ indicates the contributor was also the author of the fix; Thanks!
**** Fix dotted generated array error, bug1005. [Jeff Bush, Johan Bjork]
**** Fix error instead of warning on large concat, msg1768. [Paul Rolfe]
* Verilator 3.878 2015-11-01

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@ -978,7 +978,7 @@ V3Number& V3Number::opRepl (const V3Number& lhs, const V3Number& rhs) { // rhs i
V3Number& V3Number::opRepl (const V3Number& lhs, uint32_t rhsval) { // rhs is # of times to replicate
// i op repl, L(i)*value(rhs) bit return
setZero();
if (rhsval>8192) m_fileline->v3fatal("More than a 8k bit replication is probably wrong: "<<rhsval);
if (rhsval>8192) m_fileline->v3warn(WIDTHCONCAT,"More than a 8k bit replication is probably wrong: "<<rhsval);
int obit = 0;
for (unsigned times=0; times<rhsval; times++) {
for(int bit=0; bit<lhs.width(); bit++) {

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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2004 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

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@ -0,0 +1,19 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Wilson Snyder.
module t (/*AUTOARG*/);
wire [32767:0] a;
initial begin
// verilator lint_off WIDTHCONCAT
a = {32768{1'b1}};
// verilator lint_on WIDTHCONCAT
if (a[32000] != 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

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@ -0,0 +1,20 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2004 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
v_flags2 => ["--lint-only"],
fails=>1,
expect=>
'%Warning-WIDTHCONCAT: t/t_concat_large_bad.v:\d+: More than a 8k bit replication is probably wrong: 32768
%Warning-WIDTHCONCAT: Use .*
%Error: Exiting due to.*',
);
ok(1);
1;

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@ -0,0 +1,14 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Wilson Snyder.
module t (/*AUTOARG*/);
wire [32767:0] a = {32768{1'b1}};
initial begin
$stop;
end
endmodule