forked from github/verilator
Fix for loop missing initializer, bug1605.
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@ -4,6 +4,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
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* Verilator 4.023 devel
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**** Fix for loop missing initializer, bug1605. [Andrew Holme]
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* Verilator 4.022 2019-11-10
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@ -277,7 +277,7 @@ private:
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if (initp) {
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initp->unlinkFrBack(); // Always a single statement; nextp() may be nodep
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// Don't add to list, we do it once, and setting loop index isn't
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// needed as we're constant propagating it
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// needed if we have > 1 loop, as we're constant propagating it
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}
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if (precondsp) {
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precondsp->unlinkFrBackWithNext();
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@ -296,8 +296,8 @@ private:
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AstNode* newbodysp = NULL;
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++m_statLoops;
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int times = 0;
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if (stmtsp) {
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int times = 0;
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while (1) {
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UINFO(8," Looping "<<loopValue<<endl);
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V3Number res = V3Number(nodep);
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@ -352,6 +352,10 @@ private:
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}
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}
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}
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if (!newbodysp) { // initp might have effects after the loop
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newbodysp = initp; // Maybe NULL
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initp = NULL;
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}
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// Replace the FOR()
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if (newbodysp) nodep->replaceWith(newbodysp);
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else nodep->unlinkFrBack();
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@ -94,6 +94,13 @@ module t (/*AUTOARG*/
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for (; ; ++i) begin ++loops; break; end
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if (loops !== 1) $stop;
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//
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// bug1605
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i = 1;
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for (i=20; 0; ) ;
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if (i != 20) $stop;
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for (i=30; i<10; i++) ;
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if (i != 30) $stop;
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//
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$write("*-* All Finished *-*\n");
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$finish;
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end
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