Fix elaboration of member selected classes (#3890).

This commit is contained in:
Wilson Snyder 2023-01-19 17:44:27 -05:00
parent 317fe7a787
commit e94023367f
4 changed files with 47 additions and 0 deletions

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@ -30,6 +30,7 @@ Verilator 5.005 devel
* Fix compatibility with musl libc / Alpine Linux (#3845). [Sören Tempel]
* Fix empty case items crash (#3851). [rporter]
* Fix foreach unnamedblk duplicate error (#3885). [Ilya Barkov]
* Fix elaboration of member selected classes (#3890). [Ilya Barkov]
Verilator 5.004 2022-12-14

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@ -2581,6 +2581,7 @@ private:
} else if (AstClassRefDType* const adtypep = VN_CAST(fromDtp, ClassRefDType)) {
if (AstNode* const foundp = memberSelClass(nodep, adtypep)) {
if (AstVar* const varp = VN_CAST(foundp, Var)) {
if (!varp->didWidth()) userIterate(varp, nullptr);
nodep->dtypep(foundp->dtypep());
nodep->varp(varp);
return;

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@ -0,0 +1,21 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2023 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
);
execute(
check_finished => 1,
);
ok(1);
1;

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@ -0,0 +1,24 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
class Cls;
int t;
endclass
module Sub;
Cls c;
initial begin
int i;
c = new;
i = c.t;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module t;
Sub foo;
endmodule