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Fix order of C style arrays.

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This commit is contained in:
Wilson Snyder 2015-03-13 07:06:06 -04:00
parent 0ee5743853
commit e918d945f2
5 changed files with 51 additions and 2 deletions
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2
Changes
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@ -9,6 +9,8 @@ indicates the contributor was also the author of the fix; Thanks!
*** Add --clk and related optimizations, msg1533. [Jie Xu]
*** Fix order of C style arrays. [Duraid Madina]
**** Add --dump-treei-<srcfile>, bug894. [Jie Xu]
**** Fix comma-instantiations with parameters, bug884. [Franck Jullien]

2
src/verilog.y
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@ -1464,7 +1464,7 @@ variable_dimension<rangep>: // ==IEEE: variable_dimension
//UNSUP '[' ']' { UNSUP }
// // IEEE: unpacked_dimension
anyrange { $$ = $1; }
| '[' constExpr ']' { $$ = new AstRange($1,new AstSub($1,$2, new AstConst($1,1)), new AstConst($1,0)); }
| '[' constExpr ']' { $$ = new AstRange($1, new AstConst($1, 0), new AstSub($1, $2, new AstConst($1, 1))); }
// // IEEE: associative_dimension
//UNSUP '[' data_type ']' { UNSUP }
//UNSUP yP_BRASTAR ']' { UNSUP }

2
test_regress/t/t_mem.v
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@ -11,7 +11,7 @@ module t (/*AUTOARG*/
input clk;
integer cyc; initial cyc=1;
// [16] is SV syntax for [15:0]
// [16] is SV syntax for [0:15]
reg [7:0] memory8_16 [16];
reg m_we;

18
test_regress/t/t_unpacked_array_order.pl Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

29
test_regress/t/t_unpacked_array_order.v Normal file
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@ -0,0 +1,29 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Duraid Madina.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
parameter logic [1:0] t0 [ 2][ 2] = '{'{2'd0, 2'd1}, '{2'd2, 2'd3}};
parameter logic [1:0] t1 [0:1][0:1] = '{'{2'd0, 2'd1}, '{2'd2, 2'd3}};
parameter logic [1:0] t2 [1:0][1:0] = '{'{2'd3, 2'd2}, '{2'd1, 2'd0}};
always @ (posedge clk) begin
if (t0[0][0] != t1[0][0]) $stop;
if (t0[0][1] != t1[0][1]) $stop;
if (t0[1][0] != t1[1][0]) $stop;
if (t0[1][1] != t1[1][1]) $stop;
if (t0[0][0] != t2[0][0]) $stop;
if (t0[0][1] != t2[0][1]) $stop;
if (t0[1][0] != t2[1][0]) $stop;
if (t0[1][1] != t2[1][1]) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule