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Fix error on parameters with dotted references, bug1146.

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Wilson Snyder 2017-03-28 19:55:20 -04:00
parent c27a60658f
commit e9125a3a22
4 changed files with 45 additions and 1 deletions
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@ -29,6 +29,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
**** Fix missing error on interface size mismatch, bug1143. [Johan Bjork]
**** Fix error on parameters with dotted references, bug1146. [Johan Bjork]
* Verilator 3.900 2017-01-15

9
src/V3Width.cpp
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@ -1184,7 +1184,14 @@ private:
}
virtual void visit(AstNodeVarRef* nodep) {
if (nodep->didWidth()) return;
if (!nodep->varp()) nodep->v3fatalSrc("Unlinked varref");
if (!nodep->varp()) {
if (m_paramsOnly && nodep->castVarXRef()) {
checkConstantOrReplace(nodep, "Parameter-resolved constants must not use dotted references: "+nodep->prettyName()); VL_DANGLING(nodep);
return;
} else {
nodep->v3fatalSrc("Unlinked varref");
}
}
if (!nodep->varp()->didWidth()) {
// Var hasn't been widthed, so make it so.
userIterate(nodep->varp(), NULL);

18
test_regress/t/t_interface_param_another_bad.pl Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
fails=>1,
expect=>
q{%Error: t/t_interface_param_another_bad.v:\d+: Parameter-resolved constants must not use dotted references: dummy
%Error: Exiting due to.*},
);
ok(1);
1;

17
test_regress/t/t_interface_param_another_bad.v Normal file
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@ -0,0 +1,17 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Johan Bjork.
module t ();
simple_bus sb_intf();
simple_bus #(.PARAMETER($bits(sb_intf.dummy))) simple();
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
interface simple_bus #(PARAMETER = 0);
logic dummy;
endinterface