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Tests: Improve t_mod_interface_array4

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Wilson Snyder 2021-03-10 21:42:32 -05:00
parent 3651321679
commit e88dff6929
1 changed files with 36 additions and 35 deletions
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71
test_regress/t/t_mod_interface_array4.v
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@ -11,33 +11,6 @@ interface intf ();
integer index;
endinterface
module sub
(
input logic clk,
input int cyc,
intf alh[1:2],
intf ahl[2:1],
intf blh[1:2],
intf bhl[2:1]
);
always @(posedge clk) begin
if (cyc == 5) begin
`checkh(alh[1].index, 2);
`checkh(alh[2].index, 1);
`checkh(ahl[1].index, 1);
`checkh(ahl[2].index, 2);
`checkh(blh[1].index, 1);
`checkh(blh[2].index, 2);
`checkh(bhl[1].index, 2);
`checkh(bhl[2].index, 1);
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module t
(
clk
@ -64,15 +37,43 @@ module t
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 1) begin
ifa1_intf[1].index = 1;
ifa1_intf[2].index = 2;
ifa2_intf[1].index = 1;
ifa2_intf[2].index = 2;
ifb1_intf[1].index = 1;
ifb1_intf[2].index = 2;
ifb2_intf[1].index = 1;
ifb2_intf[2].index = 2;
ifa1_intf[1].index = 'h101;
ifa1_intf[2].index = 'h102;
ifa2_intf[1].index = 'h201;
ifa2_intf[2].index = 'h202;
ifb1_intf[1].index = 'h301;
ifb1_intf[2].index = 'h302;
ifb2_intf[1].index = 'h401;
ifb2_intf[2].index = 'h402;
end
end
endmodule
module sub
(
input logic clk,
input int cyc,
intf alh[1:2],
intf ahl[2:1],
intf blh[1:2],
intf bhl[2:1]
);
always @(posedge clk) begin
if (cyc == 5) begin
`checkh(alh[1].index, 'h102);
`checkh(alh[2].index, 'h101);
`checkh(ahl[1].index, 'h201);
`checkh(ahl[2].index, 'h202);
`checkh(blh[1].index, 'h301);
`checkh(blh[2].index, 'h302);
`checkh(bhl[1].index, 'h402);
`checkh(bhl[2].index, 'h401);
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule