Merge branch 'master' into develop-v5

Changes

@@ -19,7 +19,14 @@ Verilator 5.001 devel
   clocks are now simulated correctly (#3278, #3384). [Geza Lore, Shunyao CAD]
 
 
-Verilator 4.223 devel
+Verilator 4.225 devel
+==========================
+
+**Minor:**
+
+
+
+Verilator 4.224 2022-06-19
 ==========================
 
 **Major:**
@@ -30,16 +37,24 @@ Verilator 4.223 devel
 
 * Add -f<optimization> options to replace -O<letter> options (#3436).
 * Changed --no-merge-const-pool to -fno-merge-const-pool (#3436).
+* Changed --no-decoration to remove output whitespace (#3460). [Kamil Rakoczy]
 * Support compile time trace signal selection with tracing_on/off (#3323). [Shunyao CAD]
 * Support non-ANSI interface port declarations (#3439). [Geza Lore, Shunyao CAD]
 * Support concat assignment to packed array (#3446).
 * Improve conditional merging optimization (#3125). [Geza Lore, Shunyao CAD]
 * Define VM_TRACE_VCD when tracing in VCD format. [Geza Lore, Shunyao CAD]
 * Add assert when VerilatedContext is mis-deleted (#3121). [Rupert Swarbrick]
+* Internal prep work towards timing control. [Krzysztof Bieganski]
 * Fix hang with large case statement optimization (#3405). [Mike Urbach]
+* Fix UNOPTFLAT warning from initial static var (#3406). [Kamil Rakoczy]
+* Fix compile error when enable VL_LEAK_CHECKS (#3411). [HungMingWu]
+* Fix cmake rules to support higher-level targets (#3377) (#3386). [Martin Stadler]
+* Fix BLKANDNBLK on $readmem/$writemem (#3379). [Alex Solomatnikov]
 * Fix 'with' operator with type casting (#3387). [xiak95]
 * Fix incorrect conditional merging (#3409). [Raynard Qiao]
 * Fix passing VL_TRACE_FST_WRITER_THREAD in CMake build. [Geza Lore, Shunyao CAD]
+* Fix compile error under strict C++11 mode (#3463). [Kevin Kiningham]
+* Fix public unpacked input ports (#3465). [Todd Strader]
 
 
 Verilator 4.222 2022-05-02

configure.ac

@@ -5,14 +5,14 @@
 # General Public License Version 3 or the Perl Artistic License Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
+# When releasing, also update header of Changes file
+# and commit using "devel release" or "Version bump" message
+# Then 'make maintainer-dist'
 #AC_INIT([Verilator],[#.### YYYY-MM-DD])
 #AC_INIT([Verilator],[#.### devel])
 AC_INIT([Verilator],[5.001 devel],
         [https://verilator.org],
         [verilator],[https://verilator.org])
-# When releasing, also update header of Changes file
-# and commit using "devel release" or "Version bump" message
-# Then 'make maintainer-dist'
 
 AC_CONFIG_HEADERS(src/config_build.h)
 AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk include/verilated_config.h verilator.pc verilator-config.cmake verilator-config-version.cmake)

docs/guide/exe_verilator.rst

@@ -456,6 +456,8 @@ Summary:
 
 .. option:: -fno-merge-cond
 
+.. option:: -fno-merge-cond-motion
+
 .. option:: -fno-merge-const-pool
 
 .. option:: -fno-reloop

docs/guide/install.rst

@@ -125,6 +125,7 @@ Those developing Verilator itself may also want these (see internals.rst):
 ::
 
    sudo apt-get install gdb graphviz cmake clang clang-format-11 gprof lcov
+   sudo apt-get install yapf3
    sudo pip3 install sphinx sphinx_rtd_theme sphinxcontrib-spelling breathe
    cpan install Pod::Perldoc
    cpan install Parallel::Forker

src/V3Ast.h

@@ -2034,11 +2034,12 @@ private:
         return Default;
     }
 
-    template <typename T_Node> constexpr static void checkTypeParameter() {
+    template <typename T_Node> constexpr static bool checkTypeParameter() {
         static_assert(!std::is_const<T_Node>::value,
                       "Type parameter 'T_Node' should not be const qualified");
         static_assert(std::is_base_of<AstNode, T_Node>::value,
                       "Type parameter 'T_Node' must be a subtype of AstNode");
+        return true;
     }
 
 public:
@@ -2048,25 +2049,25 @@ public:
     // operation function in 'foreach' should be completely predictable by branch target caches in
     // modern CPUs, while it is basically unpredictable for VNVisitor.
     template <typename T_Node> void foreach (std::function<void(T_Node*)> f) {
-        checkTypeParameter<T_Node>();
+        static_assert(checkTypeParameter<T_Node>(), "Invalid type parameter 'T_Node'");
         foreachImpl<T_Node, /* VisitNext: */ false>(this, f);
     }
 
     // Same as above, but for 'const' nodes
     template <typename T_Node> void foreach (std::function<void(const T_Node*)> f) const {
-        checkTypeParameter<T_Node>();
+        static_assert(checkTypeParameter<T_Node>(), "Invalid type parameter 'T_Node'");
         foreachImpl<const T_Node, /* VisitNext: */ false>(this, f);
     }
 
     // Same as 'foreach' but also follows 'this->nextp()'
     template <typename T_Node> void foreachAndNext(std::function<void(T_Node*)> f) {
-        checkTypeParameter<T_Node>();
+        static_assert(checkTypeParameter<T_Node>(), "Invalid type parameter 'T_Node'");
         foreachImpl<T_Node, /* VisitNext: */ true>(this, f);
     }
 
     // Same as 'foreach' but also follows 'this->nextp()'
     template <typename T_Node> void foreachAndNext(std::function<void(const T_Node*)> f) const {
-        checkTypeParameter<T_Node>();
+        static_assert(checkTypeParameter<T_Node>(), "Invalid type parameter 'T_Node'");
         foreachImpl<const T_Node, /* VisitNext: */ true>(this, f);
     }
 
@@ -2075,13 +2076,13 @@ public:
     // present. Traversal is performed in some arbitrary order and is terminated as soon as the
     // result can be determined.
     template <typename T_Node> bool exists(std::function<bool(T_Node*)> p) {
-        checkTypeParameter<T_Node>();
+        static_assert(checkTypeParameter<T_Node>(), "Invalid type parameter 'T_Node'");
         return predicateImpl<T_Node, /* Default: */ false, /* VisitNext: */ false>(this, p);
     }
 
     // Same as above, but for 'const' nodes
     template <typename T_Node> void exists(std::function<bool(const T_Node*)> p) const {
-        checkTypeParameter<T_Node>();
+        static_assert(checkTypeParameter<T_Node>(), "Invalid type parameter 'T_Node'");
         return predicateImpl<const T_Node, /* Default: */ false, /* VisitNext: */ false>(this, p);
     }
 
@@ -2090,13 +2091,13 @@ public:
     // present. Traversal is performed in some arbitrary order and is terminated as soon as the
     // result can be determined.
     template <typename T_Node> bool forall(std::function<bool(T_Node*)> p) {
-        checkTypeParameter<T_Node>();
+        static_assert(checkTypeParameter<T_Node>(), "Invalid type parameter 'T_Node'");
         return predicateImpl<T_Node, /* Default: */ true, /* VisitNext: */ false>(this, p);
     }
 
     // Same as above, but for 'const' nodes
     template <typename T_Node> void forall(std::function<bool(const T_Node*)> p) const {
-        checkTypeParameter<T_Node>();
+        static_assert(checkTypeParameter<T_Node>(), "Invalid type parameter 'T_Node'");
         return predicateImpl<const T_Node, /* Default: */ true, /* VisitNext: */ false>(this, p);
     }
 

src/V3Delayed.cpp

@@ -94,6 +94,7 @@ private:
     bool m_inDly = false;  // True in delayed assignments
     bool m_inLoop = false;  // True in for loops
     bool m_inInitial = false;  // True in static initializers and initial blocks
+    bool m_ignoreBlkAndNBlk = false;  // Suppress delayed assignment BLKANDNBLK
     using VarMap = std::map<const std::pair<AstNodeModule*, std::string>, AstVar*>;
     VarMap m_modVarMap;  // Table of new var names created under module
     VDouble0 m_statSharedSet;  // Statistic tracking
@@ -105,6 +106,7 @@ private:
     void markVarUsage(AstNodeVarRef* nodep, bool blocking) {
         // Ignore if warning is disabled on this reference (used by V3Force).
         if (nodep->fileline()->warnIsOff(V3ErrorCode::BLKANDNBLK)) return;
+        if (m_ignoreBlkAndNBlk) return;
         if (blocking) nodep->user5(true);
         AstVarScope* const vscp = nodep->varScopep();
         // UINFO(4, " MVU " << blocking << " " << nodep << endl);
@@ -517,6 +519,13 @@ private:
         }
     }
 
+    virtual void visit(AstNodeReadWriteMem* nodep) override {
+        VL_RESTORER(m_ignoreBlkAndNBlk);
+        m_ignoreBlkAndNBlk = true;  // $readmem/$writemem often used in mem models
+        // so we will suppress BLKANDNBLK warnings
+        iterateChildren(nodep);
+    }
+
     virtual void visit(AstNodeFor* nodep) override {  // LCOV_EXCL_LINE
         nodep->v3fatalSrc(
             "For statements should have been converted to while statements in V3Begin");

src/V3EmitV.cpp

@@ -800,6 +800,10 @@ class EmitVPrefixedFormatter final : public V3OutFormatter {
         }
     }
 
+    virtual void putsOutput(const char* strg) override {
+        for (const char* cp = strg; *cp; cp++) putcOutput(*cp);
+    }
+
 public:
     void prefixFl(FileLine* fl) { m_prefixFl = fl; }
     FileLine* prefixFl() const { return m_prefixFl; }

src/V3File.cpp

@@ -700,6 +700,10 @@ int V3OutFormatter::endLevels(const char* strg) {
 }
 
 void V3OutFormatter::puts(const char* strg) {
+    if (!v3Global.opt.decoration()) {
+        putsOutput(strg);
+        return;
+    }
     if (m_prependIndent && strg[0] != '\n') {
         putsNoTracking(indentSpaces(endLevels(strg)));
         m_prependIndent = false;
@@ -759,13 +763,8 @@ void V3OutFormatter::puts(const char* strg) {
             break;
         case '(':
             indentInc();
-            if (v3Global.opt.decoration()) {
             // Line up continuation with open paren, plus one indent
             m_parenVec.push(m_column);
-            } else {
-                // Line up continuation with block+1
-                m_parenVec.push(m_indentLevel * m_blockIndent);
-            }
             break;
         case ')':
             if (!m_parenVec.empty()) m_parenVec.pop();
@@ -806,6 +805,7 @@ void V3OutFormatter::putBreakExpr() {
 
 // Add a line break if too wide
 void V3OutFormatter::putBreak() {
+    if (!v3Global.opt.decoration()) return;
     if (!m_nobreak) {
         // char s[1000]; sprintf(s, "{%d,%d}", m_column, m_parenVec.top()); putsNoTracking(s);
         if (exceededWidth()) {
@@ -824,11 +824,19 @@ void V3OutFormatter::putsQuoted(const string& strg) {
     putcNoTracking('"');
 }
 void V3OutFormatter::putsNoTracking(const string& strg) {
+    if (!v3Global.opt.decoration()) {
+        putsOutput(strg.c_str());
+        return;
+    }
     // Don't track {}'s, probably because it's a $display format string
     for (const char c : strg) putcNoTracking(c);
 }
 
 void V3OutFormatter::putcNoTracking(char chr) {
+    if (!v3Global.opt.decoration()) {
+        putcOutput(chr);
+        return;
+    }
     switch (chr) {
     case '\n':
         m_lineno++;

src/V3File.h

@@ -176,6 +176,7 @@ public:
 
     // CALLBACKS - MUST OVERRIDE
     virtual void putcOutput(char chr) = 0;
+    virtual void putsOutput(const char* str) = 0;
 };
 
 //============================================================================
@@ -193,6 +194,7 @@ public:
 private:
     // CALLBACKS
     virtual void putcOutput(char chr) override { fputc(chr, m_fp); }
+    virtual void putsOutput(const char* str) override { fputs(str, m_fp); }
 };
 
 class V3OutCFile VL_NOT_FINAL : public V3OutFile {

src/V3Inline.cpp

@@ -311,8 +311,8 @@ private:
                 // code will be emitted.
                 UINFO(9, "assign to public and unpacked: " << nodep << endl);
                 m_modp->addStmtp(
-                    new AstAssignW(flp, new AstVarRef(flp, exprvarrefp->varp(), VAccess::WRITE),
+                    new AstAssignW{flp, new AstVarRef{flp, nodep, VAccess::WRITE},
-                                   new AstVarRef(flp, nodep, VAccess::READ)));
+                                   new AstVarRef{flp, exprvarrefp->varp(), VAccess::READ}});
             } else if (nodep->isIfaceRef()) {
                 m_modp->addStmtp(
                     new AstAssignVarScope(flp, new AstVarRef(flp, nodep, VAccess::WRITE),

src/V3Life.cpp

@@ -218,10 +218,10 @@ public:
     void lifeToAbove() {
         // Any varrefs under a if/else branch affect statements outside and after the if/else
         if (!m_aboveLifep) v3fatalSrc("Pushing life when already at the top level");
-        for (LifeMap::iterator it = m_map.begin(); it != m_map.end(); ++it) {
+        for (auto& itr : m_map) {
-            AstVarScope* const nodep = it->first;
+            AstVarScope* const nodep = itr.first;
             m_aboveLifep->complexAssignFind(nodep);
-            if (it->second.everSet()) {
+            if (itr.second.everSet()) {
                 // Record there may be an assignment, so we don't constant propagate across the if.
                 complexAssignFind(nodep);
             } else {
@@ -235,14 +235,14 @@ public:
         // life1p->lifeDump();
         // life2p->lifeDump();
         AstNode::user1ClearTree();  // user1p() used on entire tree
-        for (LifeMap::iterator it = life1p->m_map.begin(); it != life1p->m_map.end(); ++it) {
+        for (auto& itr : life1p->m_map) {
             // When the if branch sets a var before it's used, mark that variable
-            if (it->second.setBeforeUse()) it->first->user1(1);
+            if (itr.second.setBeforeUse()) itr.first->user1(1);
         }
-        for (LifeMap::iterator it = life2p->m_map.begin(); it != life2p->m_map.end(); ++it) {
+        for (auto& itr : life2p->m_map) {
             // When the else branch sets a var before it's used
-            AstVarScope* const nodep = it->first;
+            AstVarScope* const nodep = itr.first;
-            if (it->second.setBeforeUse() && nodep->user1()) {
+            if (itr.second.setBeforeUse() && nodep->user1()) {
                 // Both branches set the var, we can remove the assignment before the IF.
                 UINFO(4, "DUALBRANCH " << nodep << endl);
                 const auto itab = m_map.find(nodep);
@@ -251,14 +251,15 @@ public:
         }
         // this->lifeDump();
     }
+    void clear() { m_map.clear(); }
     // DEBUG
     void lifeDump() {
         UINFO(5, "  LifeMap:" << endl);
-        for (LifeMap::iterator it = m_map.begin(); it != m_map.end(); ++it) {
+        for (const auto& itr : m_map) {
-            UINFO(5, "     Ent:  " << (it->second.setBeforeUse() ? "[F]  " : "     ") << it->first
+            UINFO(5, "     Ent:  " << (itr.second.setBeforeUse() ? "[F]  " : "     ") << itr.first
                                    << endl);
-            if (it->second.assignp()) {  //
+            if (itr.second.assignp()) {  //
-                UINFO(5, "       Ass: " << it->second.assignp() << endl);
+                UINFO(5, "       Ass: " << itr.second.assignp() << endl);
             }
         }
     }
@@ -283,6 +284,10 @@ private:
 
     // METHODS
     VL_DEBUG_FUNC;  // Declare debug()
+    void setNoopt() {
+        m_noopt = true;
+        m_lifep->clear();
+    }
 
     // VISITORS
     virtual void visit(AstVarRef* nodep) override {
@@ -386,13 +391,12 @@ private:
         // Just don't optimize blocks with labels; they're rare - so far.
         LifeBlock* const prevLifep = m_lifep;
         LifeBlock* const bodyLifep = new LifeBlock(prevLifep, m_statep);
-        const bool prev_noopt = m_noopt;
         {
+            VL_RESTORER(m_noopt);
             m_lifep = bodyLifep;
-            m_noopt = true;
+            setNoopt();
             iterateAndNextNull(nodep->stmtsp());
             m_lifep = prevLifep;
-            m_noopt = prev_noopt;
         }
         UINFO(4, "   joinjump" << endl);
         // For the next assignments, clear any variables that were read or written in the block

src/V3MergeCond.cpp

@@ -477,10 +477,12 @@ private:
             AstNode* currp = m_workQueuep->front();
             m_workQueuep->pop();
 
-            // Analyse sub-tree list for code motion
+            // Analyse sub-tree list for code motion and conditional merging
             CodeMotionAnalysisVisitor::analyze(currp, stmtProperties);
             // Perform the code motion within the whole sub-tree list
+            if (v3Global.opt.fMergeCondMotion()) {
                 currp = CodeMotionOptimizeVisitor::optimize(currp, stmtProperties);
+            }
 
             // Merge conditionals in the whole sub-tree list (this might create new work items)
             iterateAndNextNull(currp);

src/V3Options.cpp

@@ -1097,6 +1097,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
     DECL_OPTION("-flife-post", FOnOff, &m_fLifePost);
     DECL_OPTION("-flocalize", FOnOff, &m_fLocalize);
     DECL_OPTION("-fmerge-cond", FOnOff, &m_fMergeCond);
+    DECL_OPTION("-fmerge-cond-motion", FOnOff, &m_fMergeCondMotion);
     DECL_OPTION("-fmerge-const-pool", FOnOff, &m_fMergeConstPool);
     DECL_OPTION("-freloop", FOnOff, &m_fReloop);
     DECL_OPTION("-freorder", FOnOff, &m_fReorder);

src/V3Options.h

@@ -353,7 +353,8 @@ private:
     bool m_fLifePost;    // main switch: -fno-life-post: delayed assignment elimination
     bool m_fLocalize;    // main switch: -fno-localize: convert temps to local variables
     bool m_fMergeCond;   // main switch: -fno-merge-cond: merge conditionals
-    bool m_fMergeConstPool = true;  // main switch: --fmerge-const-pool
+    bool m_fMergeCondMotion = true; // main switch: -fno-merge-cond-motion: perform code motion
+    bool m_fMergeConstPool = true;  // main switch: -fno-merge-const-pool
     bool m_fReloop;      // main switch: -fno-reloop: reform loops
     bool m_fReorder;     // main switch: -fno-reorder: reorder assignments in blocks
     bool m_fSplit;       // main switch: -fno-split: always assignment splitting
@@ -585,6 +586,7 @@ public:
     bool fLifePost() const { return m_fLifePost; }
     bool fLocalize() const { return m_fLocalize; }
     bool fMergeCond() const { return m_fMergeCond; }
+    bool fMergeCondMotion() const { return m_fMergeCondMotion; }
     bool fMergeConstPool() const { return m_fMergeConstPool; }
     bool fReloop() const { return m_fReloop; }
     bool fReorder() const { return m_fReorder; }

test_regress/t/t_merge_cond_no_motion.pl

@@ -0,0 +1,34 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Geza Lore. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt_all => 1);
+
+top_filename("t/t_merge_cond.v");
+
+compile(
+    verilator_flags2 => ["-unroll-count 64", "--stats", "-fno-merge-cond-motion"],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+if ($Self->{vlt}) {
+    # Note, with vltmt this might be split differently, so only checking vlt
+    file_grep($Self->{stats}, qr/Optimizations, MergeCond merges\s+(\d+)/i,
+              10);
+    file_grep($Self->{stats}, qr/Optimizations, MergeCond merged items\s+(\d+)/i,
+              580);
+    file_grep($Self->{stats}, qr/Optimizations, MergeCond longest merge\s+(\d+)/i,
+              64);
+}
+
+ok(1);
+1;

test_regress/t/t_pub_unpacked_port.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Todd Strader. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(
+    vlt => 1,
+    );
+
+compile();
+execute();
+ok(1);
+1;

test_regress/t/t_pub_unpacked_port.v

@@ -0,0 +1,55 @@
+// DESCRIPTION: Verilator: Verilog Test module
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2022 by Todd Strader.
+// SPDX-License-Identifier: CC0-1.0
+
+module sub (
+   output logic [31:0] sub_s1up_out[0:0] /* verilator public_flat_rw */,
+   input logic sub_clk,
+   input logic [31:0] sub_s1up_in[0:0] /* verilator public_flat_rw */
+   );
+
+   // Evaluate clock edges
+   always @(posedge sub_clk) begin
+      sub_s1up_out <= sub_s1up_in;
+   end
+
+endmodule
+
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer cyc = 0;
+   logic   [31:0]     s1up_in[1];
+   logic   [31:0]     s1up_out[1];
+
+   sub the_sub (
+      .sub_s1up_in (s1up_in),
+      .sub_s1up_out (s1up_out),
+      .sub_clk (clk));
+
+   always_comb   s1up_in[0] = cyc;
+
+   always @(posedge clk) begin
+      cyc <= cyc + 1;
+
+      if (cyc == 10) begin
+         if (s1up_out[0] != 9) begin
+             $display("%%Error: got %0d instead of 9", s1up_out);
+             $stop;
+         end
+         if (the_sub.sub_s1up_in[0] != 10) begin
+             $display("%%Error: the_sub.sub_s1up_in was %0d instead of 10", the_sub.sub_s1up_in[0]);
+             $stop;
+         end
+         $display("final cycle = %0d", cyc);
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule

test_regress/t/t_sys_readmem_assoc.v

@@ -6,22 +6,37 @@
 
 `define STRINGIFY(x) `"x`"
 
-module t;
+module t(/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   int   cyc;
 
    reg [5:0] assoc_c[int];
    reg [95:0] assoc_w[int];
 
-   initial begin
+   always_ff @ (posedge clk) begin
-      assoc_c[300] = 10;  // See if clearing must happen first
+      cyc <= cyc + 1;
+      if (cyc == 1) begin
+         assoc_c[300] <= 10;  // See if clearing must happen first
+         // Also checks no BLKANDNBLK due to readmem/writemem
+      end
+      else if (cyc == 2) begin
          $readmemb("t/t_sys_readmem_b.mem", assoc_c);
          $display("assoc_c=%p", assoc_c);
          $writememh({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_writemem_c_b.mem"}, assoc_c);
-
+      end
+      else if (cyc == 3) begin
          $readmemb("t/t_sys_readmem_b.mem", assoc_w);
          // Not conditional with TEST_VERBOSE as found bug with wide display
          $display("assoc_w=%p", assoc_w);
          $writememh({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_writemem_w_h.mem"}, assoc_w);
+      end
+      else if (cyc == 4) begin
          $write("*-* All Finished *-*\n");
          $finish;
       end
+   end
 endmodule